From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE66-000672-LP for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHY-0004qe-44 for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:28 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:39348) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHX-0004py-UJ for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:24 -0400 Received: by mail-pa0-f41.google.com with SMTP id rd3so6288300pab.28 for ; Thu, 30 Oct 2014 14:29:23 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 16:28:41 -0500 Message-Id: <1414704538-17103-11-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Fabian Aggeler Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Update naming from c1_nsacr to nsacr to match other registers being changed. - Remove NSACR read/write functions v4 -> v5 - Changed to use renamed arm_current_el() --- target-arm/cpu.h | 6 ++++++ target-arm/helper.c | 3 +++ 2 files changed, 9 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6bb7d39..88e22fb 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ @@ -634,6 +635,11 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) +#define NSACR_NSTRCDIS (1U << 20) +#define NSACR_RFR (1U << 19) +#define NSACR_NSASEDIS (1U << 15) +#define NSACR_NSD32DIS (1U << 14) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index e73756d..3c12eb3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,9 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .resetvalue = 0, .writefn = scr_write, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3) }, + { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, + .access = PL3_RW | PL1_R, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, REGINFO_SENTINEL }; -- 1.8.3.2