From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50153) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE66-00052N-22 for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHZ-0004sW-Ho for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:30 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:59929) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHZ-0004rm-CF for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:25 -0400 Received: by mail-pa0-f49.google.com with SMTP id lj1so6236260pab.22 for ; Thu, 30 Oct 2014 14:29:24 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 16:28:42 -0500 Message-Id: <1414704538-17103-12-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v8 11/27] target-arm: add SDER definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Sergey Fedorov Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Added SDER32_EL3 register definition - Changed sder name from c1_sder to sder - Changed sder from uint32_t to uint64_t. --- target-arm/cpu.h | 1 + target-arm/helper.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 88e22fb..62cf48a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 3c12eb3..0be19f3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .resetvalue = 0, .writefn = scr_write, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3) }, + { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.sder) }, + { .name = "SDER", + .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, .access = PL3_RW | PL1_R, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, -- 1.8.3.2