From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE65-0000xb-1c for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:28:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHe-0004yR-6s for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:35 -0400 Received: from mail-pa0-f52.google.com ([209.85.220.52]:48304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHe-0004xh-1X for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:30 -0400 Received: by mail-pa0-f52.google.com with SMTP id fa1so6280121pad.39 for ; Thu, 30 Oct 2014 14:29:29 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 16:28:45 -0500 Message-Id: <1414704538-17103-15-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v8 14/27] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Fabian Aggeler bits when modifying CPSR. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Fixed incorrect use of env->uncached_cpsr A/I/F to use env->daif instead. - Removed incorrect statement about SPSR to CPSR copies being affected by SCR.AW/FW. - Fix typo in comment. - Simpified cpsr_write logic v3 -> v4 - Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and checking for the existence of EL3 and non-existence of EL2. --- target-arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 466459b..03e6b62 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3666,9 +3666,6 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) env->GE = (val >> 16) & 0xf; } - env->daif &= ~(CPSR_AIF & mask); - env->daif |= val & CPSR_AIF & mask; - if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { if (bad_mode_switch(env, val & CPSR_M)) { /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. @@ -3680,6 +3677,50 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) switch_mode(env, val & CPSR_M); } } + + /* In a V7 implementation that includes the security extensions but does + * not include Virtualization Extensions the SCR.FW and SCR.AW bits control + * whether non-secure software is allowed to change the CPSR_F and CPSR_A + * bits respectively. + * + * In a V8 implementation, it is permitted for privileged software to + * change the CPSR A/F bits regardless of the SCR.AW/FW bits. + */ + if (!arm_feature(env, ARM_FEATURE_V8) && + arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2) && + !arm_is_secure(env)) { + if (!(env->cp15.scr_el3 & SCR_AW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_A flag from " + "non-secure world with SCR.AW bit clear\n"); + mask &= ~CPSR_A; + } + + if (!(env->cp15.scr_el3 & SCR_FW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_F flag from " + "non-secure world with SCR.FW bit clear\n"); + mask &= ~CPSR_F; + } + + /* Check whether non-maskable FIQ (NMFI) support is enabled. + * If this bit is set software is not allowed to mask + * FIQs, but is allowed to set CPSR_F to 0. + */ + if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && + (val & CPSR_F)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to enable CPSR_F flag " + "(non-maskable FIQ [NMFI] support " + "enabled)\n"); + mask &= ~CPSR_F; + } + } + + env->daif &= ~(CPSR_AIF & mask); + env->daif |= val & CPSR_AIF & mask; + mask &= ~CACHED_CPSR_BITS; env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); } -- 1.8.3.2