From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE63-0006Cd-7x for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHo-0005CD-Ey for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:45 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:58361) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHo-0005Ba-9R for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:40 -0400 Received: by mail-pa0-f45.google.com with SMTP id lf10so6256757pab.18 for ; Thu, 30 Oct 2014 14:29:39 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 16:28:52 -0500 Message-Id: <1414704538-17103-22-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v8 21/27] target-arm: make DFSR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v3 -> v4 - Reverted esr/dfsr back to array-based notation as a union with v7 naming. --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 7 ++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c44649e..29bf273 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -260,7 +260,15 @@ typedef struct CPUARMState { uint32_t ifsr32_el2; }; }; - uint64_t esr_el[4]; + union { + struct { + uint64_t _unused_dfsr; + uint64_t dfsr_ns; + uint64_t hsr; + uint64_t dfsr_s; + }; + uint64_t esr_el[4]; + }; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index de355f5..c5948f7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1650,7 +1650,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), + offsetoflow32(CPUARMState, cp15.dfsr_ns) }, .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .resetvalue = 0, @@ -4309,11 +4310,11 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; case EXCP_DATA_ABORT: - env->cp15.esr_el[1] = env->exception.fsr; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - (uint32_t)env->cp15.esr_el[1], + env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x10; -- 1.8.3.2