From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org,
serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch
Cc: greg.bellows@linaro.org
Subject: [Qemu-devel] [PATCH v8 27/27] target-arm: add cpu feature EL3 to CPUs with Security Extensions
Date: Thu, 30 Oct 2014 16:28:58 -0500 [thread overview]
Message-ID: <1414704538-17103-28-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org>
From: Fabian Aggeler <aggelerf@ethz.ch>
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
target-arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a711834..d76b47e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -610,6 +610,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
@@ -696,6 +697,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
@@ -763,6 +765,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
@@ -830,6 +833,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
--
1.8.3.2
prev parent reply other threads:[~2014-10-31 15:27 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-30 21:28 [Qemu-devel] [PATCH v8 00/27] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking Greg Bellows
2014-10-31 19:00 ` Peter Maydell
2014-11-05 21:12 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 02/27] target-arm: add async excp target_el function Greg Bellows
2014-10-31 11:56 ` Peter Maydell
2014-10-31 14:14 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors Greg Bellows
2014-10-31 16:50 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 04/27] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 05/27] target-arm: add CPREG secure state support Greg Bellows
2014-10-31 12:15 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 06/27] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-31 12:28 ` Peter Maydell
2014-10-31 12:31 ` Peter Maydell
2014-10-31 16:20 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 07/27] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-31 12:44 ` Peter Maydell
2014-10-31 19:01 ` Greg Bellows
2014-11-04 22:20 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 08/27] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-31 12:06 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 09/27] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-31 12:01 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register Greg Bellows
2014-10-31 13:24 ` Peter Maydell
2014-10-31 21:09 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 11/27] target-arm: add SDER definition Greg Bellows
2014-10-31 13:30 ` Peter Maydell
2014-10-31 21:17 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support Greg Bellows
2014-10-31 13:35 ` Peter Maydell
2014-10-31 21:19 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 13/27] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-31 14:07 ` Peter Maydell
2014-10-31 21:51 ` Greg Bellows
2014-10-31 23:26 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 14/27] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-31 14:18 ` Peter Maydell
2014-11-03 14:57 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 15/27] target-arm: make CSSELR banked Greg Bellows
2014-10-31 14:23 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 16/27] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-31 15:04 ` Peter Maydell
2014-11-04 22:44 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-31 15:07 ` Peter Maydell
2014-11-04 22:45 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 18/27] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-31 15:26 ` Peter Maydell
2014-11-04 22:46 ` Greg Bellows
2014-11-04 23:27 ` Peter Maydell
2014-11-05 15:09 ` Greg Bellows
2014-11-05 15:15 ` Peter Maydell
2014-11-05 15:18 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 19/27] target-arm: make DACR banked Greg Bellows
2014-10-31 15:38 ` Peter Maydell
2014-11-03 21:23 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 20/27] target-arm: make IFSR banked Greg Bellows
2014-10-31 16:18 ` Peter Maydell
2014-11-05 22:19 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 21/27] target-arm: make DFSR banked Greg Bellows
2014-10-31 16:19 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 22/27] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-31 16:24 ` Peter Maydell
2014-11-03 22:59 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 23/27] target-arm: make PAR banked Greg Bellows
2014-10-31 17:21 ` Peter Maydell
2014-11-03 22:58 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 24/27] target-arm: make VBAR banked Greg Bellows
2014-10-31 17:22 ` Peter Maydell
2014-11-03 22:06 ` Greg Bellows
2014-11-03 22:49 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 25/27] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-31 17:27 ` Peter Maydell
2014-11-03 22:57 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 26/27] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-31 17:31 ` Peter Maydell
2014-11-03 23:00 ` Greg Bellows
2014-11-04 14:13 ` Greg Bellows
2014-10-30 21:28 ` Greg Bellows [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1414704538-17103-28-git-send-email-greg.bellows@linaro.org \
--to=greg.bellows@linaro.org \
--cc=aggelerf@ethz.ch \
--cc=edgar.iglesias@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=serge.fdrv@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).