From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE67-0006Bq-5X for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHU-0004lp-Oa for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:25 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:33778) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHU-0004kq-JI for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:20 -0400 Received: by mail-pa0-f45.google.com with SMTP id lf10so6287949pab.4 for ; Thu, 30 Oct 2014 14:29:19 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 16:28:39 -0500 Message-Id: <1414704538-17103-9-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v8 08/27] target-arm: move AArch32 SCR into security reglist List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Fabian Aggeler Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving AArch32 SCR into Security Extension register group. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Fix SCR register fieldoffset to be offsetoflow32. - Rename v7_el3_cp_reginfo to el3_cp_reginfo and remove v7 feature check when defining. This allows all common v7/8 secure CP regs to be registered together leaving the v8_el3_cp_reginfo to only v8 specific EL3 registers. - Move SCR_EL3 into el3_cp_reginfo. v4 -> v5 - Added reset value on SCR_EL3 - Squashed SCR Migration fix (previously patch 33) This patch adds code to mark duplicate CP register registrations as NO_MIGRATE to avoid duplicate migrations. v3 -> v4 - Renamed security_cp_reginfo to v7_el3_cp_reginfo - Conditionalized define on whether v7 or v8 were enabled --- target-arm/helper.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c1c6303..3fdd3c2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -898,9 +898,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .resetvalue = 0, .writefn = scr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2335,11 +2332,18 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .writefn = scr_write }, + .resetvalue = 0, .writefn = scr_write }, + { .name = "SCR", .type = ARM_CP_NO_MIGRATE, + .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL3_RW, .resetvalue = 0, .writefn = scr_write, + .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3) }, REGINFO_SENTINEL }; @@ -2960,7 +2964,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } if (arm_feature(env, ARM_FEATURE_EL3)) { - define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } + define_arm_cp_regs(cpu, el3_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new -- 1.8.3.2