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From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch,
	christoffer.dall@linaro.org
Cc: daniel.thompson@linaro.org
Subject: [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR
Date: Thu, 30 Oct 2014 17:12:06 -0500	[thread overview]
Message-ID: <1414707132-24588-11-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org>

From: Fabian Aggeler <aggelerf@ethz.ch>

For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
 hw/intc/arm_gic.c      | 17 ++++++++++++++++-
 hw/intc/gic_internal.h |  1 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 3761d12..9b021d7 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -314,6 +314,21 @@ void gic_set_cpu_control(GICState *s, int cpu, uint32_t value)
     }
 }
 
+uint8_t gic_get_running_priority(GICState *s, int cpu)
+{
+    if (s->security_extn && ns_access()) {
+        if (s->running_priority[cpu] & 0x80) {
+            /* Running priority in upper half, return Non-secure view */
+            return s->running_priority[cpu] << 1;
+        } else {
+            /* Running priority in lower half, RAZ */
+            return 0;
+        }
+    } else {
+        return s->running_priority[cpu];
+    }
+}
+
 void gic_complete_irq(GICState *s, int cpu, int irq)
 {
     int update = 0;
@@ -849,7 +864,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset)
     case 0x0c: /* Acknowledge */
         return gic_acknowledge_irq(s, cpu);
     case 0x14: /* Running Priority */
-        return s->running_priority[cpu];
+        return gic_get_running_priority(s, cpu);
     case 0x18: /* Highest Pending Interrupt */
         return s->current_pending[cpu];
     case 0x1c: /* Aliased Binary Point */
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index e360de6..821ce16 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -78,6 +78,7 @@ void gic_init_irqs_and_distributor(GICState *s);
 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val);
 uint32_t gic_get_cpu_control(GICState *s, int cpu);
 void gic_set_cpu_control(GICState *s, int cpu, uint32_t value);
+uint8_t gic_get_running_priority(GICState *s, int cpu);
 
 
 static inline bool gic_test_pending(GICState *s, int irq, int cm)
-- 
1.8.3.2

  parent reply	other threads:[~2014-10-31 15:26 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-30 22:11 [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping Greg Bellows
2014-10-30 22:11 ` [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources Greg Bellows
2015-04-14 18:46   ` Peter Maydell
2014-10-30 22:11 ` [Qemu-devel] [PATCH v2 02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Greg Bellows
2015-04-14 18:48   ` Peter Maydell
2014-10-30 22:11 ` [Qemu-devel] [PATCH v2 03/16] hw/arm/virt.c: " Greg Bellows
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property Greg Bellows
2015-04-14 18:51   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 05/16] hw/intc/arm_gic: Add ns_access() function Greg Bellows
2015-04-14 18:53   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 06/16] hw/intc/arm_gic: Add Interrupt Group Registers Greg Bellows
2015-04-14 19:13   ` Peter Maydell
2015-04-17 17:33     ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked Greg Bellows
2014-11-04 14:46   ` Daniel Thompson
2014-11-04 18:35     ` Greg Bellows
2015-04-14 19:18   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked Greg Bellows
2015-04-14 19:22   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked Greg Bellows
2015-04-14 19:23   ` Peter Maydell
2014-10-30 22:12 ` Greg Bellows [this message]
2015-04-14 19:24   ` [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR Greg Bellows
2015-04-14 19:25   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes Greg Bellows
2015-04-14 19:30   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR writes Greg Bellows
2015-04-14 19:31   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 14/16] hw/intc/arm_gic: Restrict priority view Greg Bellows
2015-04-14 19:32   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 15/16] hw/intc/arm_gic: Break out gic_update() function Greg Bellows
2015-04-14 19:36   ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 16/16] hw/intc/arm_gic: add gic_update() for grouping Greg Bellows
2014-11-07 12:44   ` Daniel Thompson
2014-11-10 14:43     ` Greg Bellows
2014-11-10 16:13       ` Christoffer Dall
2015-04-14 19:39   ` Peter Maydell
2015-04-14 19:18 ` [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping Peter Maydell

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