From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51047) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE4x-00062Z-IM for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:26:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xjxxd-0006Bj-IV for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:59 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:45660) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xjxxd-0006BB-CR for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:53 -0400 Received: by mail-pd0-f182.google.com with SMTP id fp1so6008465pdb.27 for ; Thu, 30 Oct 2014 15:12:52 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 17:12:06 -0500 Message-Id: <1414707132-24588-11-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> References: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, christoffer.dall@linaro.org Cc: daniel.thompson@linaro.org From: Fabian Aggeler For GICs with Security Extensions Non-secure reads have a restricted view on the current running priority. Signed-off-by: Fabian Aggeler --- hw/intc/arm_gic.c | 17 ++++++++++++++++- hw/intc/gic_internal.h | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 3761d12..9b021d7 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -314,6 +314,21 @@ void gic_set_cpu_control(GICState *s, int cpu, uint32_t value) } } +uint8_t gic_get_running_priority(GICState *s, int cpu) +{ + if (s->security_extn && ns_access()) { + if (s->running_priority[cpu] & 0x80) { + /* Running priority in upper half, return Non-secure view */ + return s->running_priority[cpu] << 1; + } else { + /* Running priority in lower half, RAZ */ + return 0; + } + } else { + return s->running_priority[cpu]; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -849,7 +864,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x0c: /* Acknowledge */ return gic_acknowledge_irq(s, cpu); case 0x14: /* Running Priority */ - return s->running_priority[cpu]; + return gic_get_running_priority(s, cpu); case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index e360de6..821ce16 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -78,6 +78,7 @@ void gic_init_irqs_and_distributor(GICState *s); void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); uint32_t gic_get_cpu_control(GICState *s, int cpu); void gic_set_cpu_control(GICState *s, int cpu, uint32_t value); +uint8_t gic_get_running_priority(GICState *s, int cpu); static inline bool gic_test_pending(GICState *s, int irq, int cm) -- 1.8.3.2