From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE4v-00026K-LX for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:26:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xjxxk-0006KI-Ro for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:13:06 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:43530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xjxxk-0006Jb-Mi for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:13:00 -0400 Received: by mail-pa0-f49.google.com with SMTP id lj1so6318867pab.36 for ; Thu, 30 Oct 2014 15:13:00 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 17:12:11 -0500 Message-Id: <1414707132-24588-16-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> References: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v2 15/16] hw/intc/arm_gic: Break out gic_update() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, christoffer.dall@linaro.org Cc: daniel.thompson@linaro.org From: Fabian Aggeler Prepare to split gic_update() in two functions, one for GICs with interrupt grouping and one without grouping (existing). Signed-off-by: Fabian Aggeler --- hw/intc/arm_gic.c | 11 ++++++++--- hw/intc/gic_internal.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index e01cfdc..808aa18 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -52,9 +52,7 @@ static inline bool ns_access(void) return true; } -/* TODO: Many places that call this routine could be optimized. */ -/* Update interrupt status after enabled or pending bits have been changed. */ -void gic_update(GICState *s) +inline void gic_update_no_grouping(GICState *s) { int best_irq; int best_prio; @@ -93,6 +91,13 @@ void gic_update(GICState *s) } } +/* TODO: Many places that call this routine could be optimized. */ +/* Update interrupt status after enabled or pending bits have been changed. */ +void gic_update(GICState *s) +{ + gic_update_no_grouping(s); +} + void gic_set_pending_private(GICState *s, int cpu, int irq) { int cm = 1 << cpu; diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 13fe5a6..e16a7e5 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -73,6 +73,7 @@ void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); +inline void gic_update_no_grouping(GICState *s); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s); void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); -- 1.8.3.2