From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE4z-0005NK-NU for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:26:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxxP-0005vc-QE for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:45 -0400 Received: from mail-pd0-f181.google.com ([209.85.192.181]:48375) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxxP-0005v2-KH for qemu-devel@nongnu.org; Thu, 30 Oct 2014 18:12:39 -0400 Received: by mail-pd0-f181.google.com with SMTP id y10so5991498pdj.12 for ; Thu, 30 Oct 2014 15:12:39 -0700 (PDT) From: Greg Bellows Date: Thu, 30 Oct 2014 17:11:57 -0500 Message-Id: <1414707132-24588-2-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> References: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, christoffer.dall@linaro.org Cc: daniel.thompson@linaro.org From: Fabian Aggeler Preparing for FIQ lines from GIC to CPUs, which is needed for GIC Security Extensions. Signed-off-by: Fabian Aggeler --- hw/intc/arm_gic.c | 3 +++ include/hw/intc/arm_gic_common.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 270ce05..ea05f8f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -789,6 +789,9 @@ void gic_init_irqs_and_distributor(GICState *s) for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(sbd, &s->parent_irq[i]); } + for (i = 0; i < NUM_CPU(s); i++) { + sysbus_init_irq(sbd, &s->parent_fiq[i]); + } memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, "gic_dist", 0x1000); } diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index f6887ed..01c6f24 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -50,6 +50,7 @@ typedef struct GICState { /*< public >*/ qemu_irq parent_irq[GIC_NCPU]; + qemu_irq parent_fiq[GIC_NCPU]; bool enabled; bool cpu_enabled[GIC_NCPU]; -- 1.8.3.2