From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org,
serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch,
christoffer.dall@linaro.org
Cc: daniel.thompson@linaro.org
Subject: [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property
Date: Thu, 30 Oct 2014 17:12:00 -0500 [thread overview]
Message-ID: <1414707132-24588-5-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1414707132-24588-1-git-send-email-greg.bellows@linaro.org>
From: Fabian Aggeler <aggelerf@ethz.ch>
The existing implementation does not support Security Extensions mentioned
in the GICv1 and GICv2 architecture specification. Security Extensions are
not available on all GICs. This property makes it possible to enable Security Extensions.
It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement
Security Extensions.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
v1 -> v2
- Change GICState security extension property from a uint8 type to bool
---
hw/intc/arm_gic.c | 5 ++++-
hw/intc/arm_gic_common.c | 1 +
include/hw/intc/arm_gic_common.h | 1 +
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index ea05f8f..0ee7778 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -298,7 +298,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
if (offset == 0)
return s->enabled;
if (offset == 4)
- return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
+ /* Interrupt Controller Type Register */
+ return ((s->num_irq / 32) - 1)
+ | ((NUM_CPU(s) - 1) << 5)
+ | (s->security_extn << 10);
if (offset < 0x08)
return 0;
if (offset >= 0x80) {
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index 18b01ba..e35049d 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = {
* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
*/
DEFINE_PROP_UINT32("revision", GICState, revision, 1),
+ DEFINE_PROP_BOOL("security-extn", GICState, security_extn, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index 01c6f24..7825134 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -105,6 +105,7 @@ typedef struct GICState {
MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
uint32_t num_irq;
uint32_t revision;
+ bool security_extn;
int dev_fd; /* kvm device fd if backed by kvm vgic support */
} GICState;
--
1.8.3.2
next prev parent reply other threads:[~2014-10-31 15:26 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-30 22:11 [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping Greg Bellows
2014-10-30 22:11 ` [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources Greg Bellows
2015-04-14 18:46 ` Peter Maydell
2014-10-30 22:11 ` [Qemu-devel] [PATCH v2 02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Greg Bellows
2015-04-14 18:48 ` Peter Maydell
2014-10-30 22:11 ` [Qemu-devel] [PATCH v2 03/16] hw/arm/virt.c: " Greg Bellows
2014-10-30 22:12 ` Greg Bellows [this message]
2015-04-14 18:51 ` [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 05/16] hw/intc/arm_gic: Add ns_access() function Greg Bellows
2015-04-14 18:53 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 06/16] hw/intc/arm_gic: Add Interrupt Group Registers Greg Bellows
2015-04-14 19:13 ` Peter Maydell
2015-04-17 17:33 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked Greg Bellows
2014-11-04 14:46 ` Daniel Thompson
2014-11-04 18:35 ` Greg Bellows
2015-04-14 19:18 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked Greg Bellows
2015-04-14 19:22 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked Greg Bellows
2015-04-14 19:23 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR Greg Bellows
2015-04-14 19:24 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR Greg Bellows
2015-04-14 19:25 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes Greg Bellows
2015-04-14 19:30 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR writes Greg Bellows
2015-04-14 19:31 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 14/16] hw/intc/arm_gic: Restrict priority view Greg Bellows
2015-04-14 19:32 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 15/16] hw/intc/arm_gic: Break out gic_update() function Greg Bellows
2015-04-14 19:36 ` Peter Maydell
2014-10-30 22:12 ` [Qemu-devel] [PATCH v2 16/16] hw/intc/arm_gic: add gic_update() for grouping Greg Bellows
2014-11-07 12:44 ` Daniel Thompson
2014-11-10 14:43 ` Greg Bellows
2014-11-10 16:13 ` Christoffer Dall
2015-04-14 19:39 ` Peter Maydell
2015-04-14 19:18 ` [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping Peter Maydell
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