From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlKF5-0004LO-W1 for qemu-devel@nongnu.org; Mon, 03 Nov 2014 11:12:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlKF0-0005Ux-Qx for qemu-devel@nongnu.org; Mon, 03 Nov 2014 11:12:31 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:6124) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlKF0-0005Uq-LQ for qemu-devel@nongnu.org; Mon, 03 Nov 2014 11:12:26 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id B9CD771EE89CE for ; Mon, 3 Nov 2014 16:12:22 +0000 (GMT) From: Leon Alrae Date: Mon, 3 Nov 2014 16:11:17 +0000 Message-ID: <1415031108-15039-4-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1415031108-15039-1-git-send-email-leon.alrae@imgtec.com> References: <1415031108-15039-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 03/34] target-mips: distinguish between data load and instruction fetch List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Leon Alrae Reviewed-by: Yongbok Kim --- target-mips/helper.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target-mips/helper.c b/target-mips/helper.c index fe16820..1c9e69d 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -87,7 +87,7 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, /* Check access rights */ if (!(n ? tlb->V1 : tlb->V0)) return TLBRET_INVALID; - if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { + if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *physical = tlb->PFN[n] | (address & (mask >> 1)); *prot = PAGE_READ; if (n ? tlb->D1 : tlb->D0) @@ -237,25 +237,28 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, case TLBRET_BADADDR: /* Reference to kernel address from user mode or supervisor mode */ /* Reference to supervisor address from user mode */ - if (rw) + if (rw == MMU_DATA_STORE) { exception = EXCP_AdES; - else + } else { exception = EXCP_AdEL; + } break; case TLBRET_NOMATCH: /* No TLB match for a mapped address */ - if (rw) + if (rw == MMU_DATA_STORE) { exception = EXCP_TLBS; - else + } else { exception = EXCP_TLBL; + } error_code = 1; break; case TLBRET_INVALID: /* TLB match with no valid bit */ - if (rw) + if (rw == MMU_DATA_STORE) { exception = EXCP_TLBS; - else + } else { exception = EXCP_TLBL; + } break; case TLBRET_DIRTY: /* TLB match but 'D' bit is cleared */ @@ -312,8 +315,6 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, env->active_tc.PC, address, rw, mmu_idx); - rw &= 1; - /* data access */ #if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() @@ -347,8 +348,6 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r int access_type; int ret = 0; - rw &= 1; - /* data access */ access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, -- 2.1.0