[Qemu-devel] [PATCH 0/7] target-ppc: Assorted Floating Point Bugs and Cleanup

[Tom Musta <tommusta@gmail.com>]

This patch series corrects some issues with floating point emulation
on Power.

Patch 1 corrects a corner case in the square root instructions, which
incorrectly react to NaNs whose sign bit is a 1.

Patches 2-6 correct a pervasive problem with modeling of the CR[1]
field (i.e. the so-called "dot form" instructions of the FPU).

The bugs were found by running random test patterns through actual Power
hardware (P7 and P8) and comparing against QEMU.

The patches conflict quite a bit with Paolo's series that splits CR into
32 one bit registers.  Paolo: is V3 of your patch series coming anytime 
soon?

Tom Musta (7):
  target-ppc: VXSQRT Should Not Be Set for NaNs
  target-ppc: Introduce gen_set_cr1_from_fpscr
  target-ppc: Fix Floating Point Move Instructions That Set CR1
  target-ppc: mffs. Should Set CR1 from FPSCR Bits
  target-ppc: Fully Migrate to gen_set_cr1_from_fpscr
  target-ppc: Eliminate set_fprf Argument From gen_compute_fprf
  target-ppc: Eliminate set_fprf Argument From helper_compute_fprf

 target-ppc/fpu_helper.c |   85 +++++++++++++++++++-------------------
 target-ppc/helper.h     |    2 +-
 target-ppc/translate.c  |  105 +++++++++++++++++++++++++++++++----------------
 3 files changed, 113 insertions(+), 79 deletions(-)