From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44890) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlNpN-0005fN-0V for qemu-devel@nongnu.org; Mon, 03 Nov 2014 15:02:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlNpE-00026T-0H for qemu-devel@nongnu.org; Mon, 03 Nov 2014 15:02:12 -0500 From: Tom Musta Date: Mon, 3 Nov 2014 14:01:12 -0600 Message-Id: <1415044877-17300-3-git-send-email-tommusta@gmail.com> In-Reply-To: <1415044877-17300-1-git-send-email-tommusta@gmail.com> References: <1415044877-17300-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 2/7] target-ppc: Introduce gen_set_cr1_from_fpscr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: pbonzini@redhat.com, agraf@suse.de, Tom Musta The Power ISA supports a mode in many floating point instructions whereby the Condition Register field 1 (CR[1]) receives a copy of the Floating Point Status (FPSCR) bits 32:35, also known as FX, FEX VX and OX. The existing QEMU code is mostly wrong -- CR[1] is set to the Floating Point Condition Code (FPSCR[FPCC]). Furthermore, this code is buried inside the code that generates the FPSCR[FPRF] code, which is awkward. Introduce a new generator utility that correctly sets CR[1] from the FPSCR bits. Subsequent patches will correct various segments of the defective code and will clean up the gen_compute_fprf() utility. Signed-off-by: Tom Musta --- target-ppc/translate.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d03daea..7775bf4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -249,6 +249,14 @@ static inline void gen_reset_fpstatus(void) gen_helper_reset_fpstatus(cpu_env); } +static inline void gen_set_cr1_from_fpscr(void) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], t0, 28); + tcg_temp_free_i32(t0); +} + static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) { TCGv_i32 t0 = tcg_temp_new_i32(); -- 1.7.1