From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44936) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlNpU-0005gq-1B for qemu-devel@nongnu.org; Mon, 03 Nov 2014 15:02:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlNpG-000270-CM for qemu-devel@nongnu.org; Mon, 03 Nov 2014 15:02:19 -0500 From: Tom Musta Date: Mon, 3 Nov 2014 14:01:14 -0600 Message-Id: <1415044877-17300-5-git-send-email-tommusta@gmail.com> In-Reply-To: <1415044877-17300-1-git-send-email-tommusta@gmail.com> References: <1415044877-17300-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 4/7] target-ppc: mffs. Should Set CR1 from FPSCR Bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: pbonzini@redhat.com, agraf@suse.de, Tom Musta Update the Move From FPSCR (mffs.) instruction to correctly set CR[1] from FPSCR[FX,FEX,VX,OX]. Signed-off-by: Tom Musta --- target-ppc/translate.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9653ba9..0247af5 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2512,7 +2512,9 @@ static void gen_mffs(DisasContext *ctx) } gen_reset_fpstatus(); tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(); + } } /* mtfsb0 */ -- 1.7.1