From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44939) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlNpU-0005h4-3d for qemu-devel@nongnu.org; Mon, 03 Nov 2014 15:02:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlNpH-000278-Kt for qemu-devel@nongnu.org; Mon, 03 Nov 2014 15:02:20 -0500 From: Tom Musta Date: Mon, 3 Nov 2014 14:01:15 -0600 Message-Id: <1415044877-17300-6-git-send-email-tommusta@gmail.com> In-Reply-To: <1415044877-17300-1-git-send-email-tommusta@gmail.com> References: <1415044877-17300-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 5/7] target-ppc: Fully Migrate to gen_set_cr1_from_fpscr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: pbonzini@redhat.com, agraf@suse.de, Tom Musta Eliminate the set_rc argument from the gen_compute_fprf utility and the corresponding (and incorrect) implementation. Replace it with calls to the gen_set_cr1_from_fpscr() utility. Signed-off-by: Tom Musta --- target-ppc/translate.c | 55 ++++++++++++++++++++++++++++------------------- 1 files changed, 33 insertions(+), 22 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0247af5..d719cdf 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -257,7 +257,7 @@ static inline void gen_set_cr1_from_fpscr(void) tcg_temp_free_i32(t0); } -static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) +static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf) { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -265,15 +265,7 @@ static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) /* This case might be optimized later */ tcg_gen_movi_i32(t0, 1); gen_helper_compute_fprf(t0, cpu_env, arg, t0); - if (unlikely(set_rc)) { - tcg_gen_mov_i32(cpu_crf[1], t0); - } gen_helper_float_check_status(cpu_env); - } else if (unlikely(set_rc)) { - /* We always need to compute fpcc */ - tcg_gen_movi_i32(t0, 0); - gen_helper_compute_fprf(t0, cpu_env, arg, t0); - tcg_gen_mov_i32(cpu_crf[1], t0); } tcg_temp_free_i32(t0); @@ -2116,8 +2108,10 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rD(ctx->opcode)]); \ } \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ - Rc(ctx->opcode) != 0); \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(); \ + } \ } #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ @@ -2141,8 +2135,10 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rD(ctx->opcode)]); \ } \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(); \ + } \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ @@ -2165,8 +2161,10 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rD(ctx->opcode)]); \ } \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(); \ + } \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ @@ -2184,8 +2182,10 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rB(ctx->opcode)]); \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(); \ + } \ } #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ @@ -2200,8 +2200,10 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rB(ctx->opcode)]); \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(); \ + } \ } /* fadd - fadds */ @@ -2234,7 +2236,10 @@ static void gen_frsqrtes(DisasContext *ctx) cpu_fpr[rB(ctx->opcode)]); gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(); + } } /* fsel */ @@ -2255,7 +2260,10 @@ static void gen_fsqrt(DisasContext *ctx) gen_reset_fpstatus(); gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, cpu_fpr[rB(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(); + } } static void gen_fsqrts(DisasContext *ctx) @@ -2271,7 +2279,10 @@ static void gen_fsqrts(DisasContext *ctx) cpu_fpr[rB(ctx->opcode)]); gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(); + } } /*** Floating-Point multiply-and-add ***/ -- 1.7.1