From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36352) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xljkw-00021m-G6 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 14:27:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xljkk-0007xv-D3 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 14:27:06 -0500 From: Alexander Graf Date: Tue, 4 Nov 2014 20:26:22 +0100 Message-Id: <1415129211-9740-5-git-send-email-agraf@suse.de> In-Reply-To: <1415129211-9740-1-git-send-email-agraf@suse.de> References: <1415129211-9740-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 04/33] ppc: rename gen_set_cr6_from_fpscr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Paolo Bonzini From: Paolo Bonzini It sets CR1, not CR6 (and the spec agrees). Signed-off-by: Paolo Bonzini Reviewed-by: Tom Musta Tested-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d03daea..d1deba7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8221,7 +8221,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) } #if defined(TARGET_PPC64) -static void gen_set_cr6_from_fpscr(DisasContext *ctx) +static void gen_set_cr1_from_fpscr(DisasContext *ctx) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); @@ -8229,7 +8229,7 @@ static void gen_set_cr6_from_fpscr(DisasContext *ctx) tcg_temp_free_i32(tmp); } #else -static void gen_set_cr6_from_fpscr(DisasContext *ctx) +static void gen_set_cr1_from_fpscr(DisasContext *ctx) { tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); } @@ -8249,7 +8249,7 @@ static void gen_##name(DisasContext *ctx) \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_env, rd, ra, rb); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rd); \ tcg_temp_free_ptr(ra); \ @@ -8307,7 +8307,7 @@ static void gen_##name(DisasContext *ctx) \ u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rb); \ @@ -8331,7 +8331,7 @@ static void gen_##name(DisasContext *ctx) \ i32 = tcg_const_i32(i32fld(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, ra, rb, i32); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rb); \ @@ -8352,7 +8352,7 @@ static void gen_##name(DisasContext *ctx) \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rb); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rb); \ @@ -8373,7 +8373,7 @@ static void gen_##name(DisasContext *ctx) \ i32 = tcg_const_i32(i32fld(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rs, i32); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rs); \ -- 1.8.1.4