From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xljkv-00021e-Tj for qemu-devel@nongnu.org; Tue, 04 Nov 2014 14:27:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xljkk-0007yQ-R8 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 14:27:05 -0500 From: Alexander Graf Date: Tue, 4 Nov 2014 20:26:23 +0100 Message-Id: <1415129211-9740-6-git-send-email-agraf@suse.de> In-Reply-To: <1415129211-9740-1-git-send-email-agraf@suse.de> References: <1415129211-9740-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 05/33] ppc: compute mask from BI using right shift List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Paolo Bonzini From: Paolo Bonzini This will match the code we use in fpu_helper.c when we flip CRF_* bit-endianness. Signed-off-by: Paolo Bonzini Reviewed-by: Tom Musta Tested-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d1deba7..ff0dc13 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -784,7 +784,7 @@ static void gen_isel(DisasContext *ctx) l1 = gen_new_label(); l2 = gen_new_label(); - mask = 1 << (3 - (bi & 0x03)); + mask = 0x08 >> (bi & 0x03); t0 = tcg_temp_new_i32(); tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); @@ -3889,7 +3889,7 @@ static inline void gen_bcond(DisasContext *ctx, int type) if ((bo & 0x10) == 0) { /* Test CR */ uint32_t bi = BI(ctx->opcode); - uint32_t mask = 1 << (3 - (bi & 0x03)); + uint32_t mask = 0x08 >> (bi & 0x03); TCGv_i32 temp = tcg_temp_new_i32(); if (bo & 0x8) { @@ -3971,7 +3971,7 @@ static void glue(gen_, name)(DisasContext *ctx) else \ tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ tcg_op(t0, t0, t1); \ - bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ + bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ tcg_gen_andi_i32(t0, t0, bitmask); \ tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ -- 1.8.1.4