From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlxKF-0003Ar-Ti for qemu-devel@nongnu.org; Wed, 05 Nov 2014 04:56:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlxK5-0004Nx-C0 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 04:56:27 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39416 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlxK5-0004Nf-6D for qemu-devel@nongnu.org; Wed, 05 Nov 2014 04:56:17 -0500 From: Alexander Graf Date: Wed, 5 Nov 2014 10:56:15 +0100 Message-Id: <1415181375-112604-3-git-send-email-agraf@suse.de> In-Reply-To: <1415181375-112604-1-git-send-email-agraf@suse.de> References: <1415181375-112604-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 2/2] s390x: Implement SAM{24,31,64} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, kbastian@mail.uni-paderborn.de, rth@twiddle.net The SAM instructions simply change 2 bits in PSW.MASK to advertise the current memory mode. While we can't fully guarantee that 31 bit mode (or even remotely 24 bit mode) actually work correctly, we don't check whether lpswe modifies these bits, so we shouldn't keep the guest from executing SAM instructions either. This patch implements all SAM instrutions with their actual PSW changing semantics, making more recent Linux kernels boot properly which do issue a SAM31 call during early boot. Signed-off-by: Alexander Graf Reviewed-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-s390x/insn-data.def | 6 +++--- target-s390x/translate.c | 12 ++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index b42ebb6..4d2feb6 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -744,9 +744,9 @@ /* SERVICE CALL LOGICAL PROCESSOR (PV hypercall) */ C(0xb220, SERVC, RRE, Z, r1_o, r2_o, 0, 0, servc, 0) /* SET ADDRESSING MODE */ - /* We only do 64-bit, so accept this as a no-op. - Let SAM24 and SAM31 signal illegal instruction. */ - C(0x010e, SAM64, E, Z, 0, 0, 0, 0, 0, 0) + D(0x010c, SAM24, E, Z, 0, 0, 0, 0, sam, 0, 0) + D(0x010d, SAM31, E, Z, 0, 0, 0, 0, sam, 0, 1) + D(0x010e, SAM64, E, Z, 0, 0, 0, 0, sam, 0, 3) /* SET ADDRESS SPACE CONTROL FAST */ C(0xb279, SACF, S, Z, 0, a2, 0, 0, sacf, 0) /* SET CLOCK */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 0cb036f..827cda4 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2927,6 +2927,18 @@ static ExitStatus op_sacf(DisasContext *s, DisasOps *o) } #endif +static ExitStatus op_sam(DisasContext *s, DisasOps *o) +{ + int sam = s->insn->data; + TCGv_i64 tsam = tcg_const_i64(sam); + + /* Overwrite PSW_MASK_64 and PSW_MASK_32 */ + tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); + + tcg_temp_free_i64(tsam); + return EXIT_PC_STALE; +} + static ExitStatus op_sar(DisasContext *s, DisasOps *o) { int r1 = get_field(s->fields, r1); -- 1.7.12.4