From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm8Wx-0003su-Q5 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 16:54:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm8Wr-00076r-MQ for qemu-devel@nongnu.org; Wed, 05 Nov 2014 16:54:19 -0500 Received: from mx1.redhat.com ([209.132.183.28]:58159) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm8Wr-00075c-F0 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 16:54:13 -0500 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Date: Wed, 5 Nov 2014 22:53:32 +0100 Message-Id: <1415224413-13972-3-git-send-email-rkrcmar@redhat.com> In-Reply-To: <1415224413-13972-1-git-send-email-rkrcmar@redhat.com> References: <1415224413-13972-1-git-send-email-rkrcmar@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 2/3] target-i386: introduce x86_cpu_nr_apic_ids List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?UTF-8?q?Andreas=20F=C3=A4rber?= The number of available APIC IDs depends on chosen topology, because core/smt choices different from a power of two waste some IDs. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- target-i386/cpu.c | 16 ++++++++++++++++ target-i386/cpu.h | 1 + 2 files changed, 17 insertions(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index e194601..c77ec76 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2815,6 +2815,22 @@ uint32_t x86_cpu_apic_id_from_index(unsigned int c= pu_index) } } =20 +/* The number of useable APIC IDs based on current topology. + * + * id_limit is the highest possible APIC ID + 1. + */ +unsigned x86_cpu_nr_apic_ids(unsigned id_limit) +{ + unsigned package_width; + + if (compat_apic_id_mode) + return id_limit; + + package_width =3D apicid_pkg_width(smp_cores, smp_threads, id_limit)= ; + + return MIN(id_limit, (1 << package_width) * smp_cores * smp_threads)= ; +} + static void x86_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 9f01831..367968d 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1372,6 +1372,7 @@ void x86_cpu_compat_disable_kvm_features(FeatureWor= d w, uint32_t features); const char *get_register_name_32(unsigned int reg); =20 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index); +unsigned x86_cpu_nr_apic_ids(unsigned id_limit); void enable_compat_apic_id_mode(void); =20 #define APIC_DEFAULT_ADDRESS 0xfee00000 --=20 2.1.0