From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56355) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vT-0004EI-8s for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vN-0004dJ-0Z for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:43 -0500 Received: from mail-pa0-f46.google.com ([209.85.220.46]:57751) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vM-0004dB-SG for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:36 -0500 Received: by mail-pa0-f46.google.com with SMTP id lf10so1747949pab.19 for ; Wed, 05 Nov 2014 15:23:36 -0800 (PST) From: Greg Bellows Date: Wed, 5 Nov 2014 17:22:57 -0600 Message-Id: <1415229793-3278-11-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v9 10/26] target-arm: add NSACR register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Cc: greg.bellows@linaro.org From: Fabian Aggeler Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Removed unused NSACR constants - Added TODO for trapping secure EL1 accesses to NSACR - Change NSACR access from PL3_RW to PL3_W - Fixed declaration order of the NSACR register components v7 -> v8 - Update naming from c1_nsacr to nsacr to match other registers being changed. - Remove NSACR read/write functions v4 -> v5 - Changed to use renamed arm_current_el() --- target-arm/cpu.h | 1 + target-arm/helper.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3031911..d2db3aa 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 3086c2c..016cf39 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ + { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL3_W | PL1_R, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, REGINFO_SENTINEL }; -- 1.8.3.2