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From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, serge.fdrv@gmail.com,
	edgar.iglesias@gmail.com, aggelerf@ethz.ch,
	peter.maydell@linaro.org
Cc: greg.bellows@linaro.org
Subject: [Qemu-devel] [PATCH v9 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions
Date: Wed,  5 Nov 2014 17:23:13 -0600	[thread overview]
Message-ID: <1415229793-3278-27-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org>

From: Fabian Aggeler <aggelerf@ethz.ch>

Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
 target-arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 53b311a..4c36e2e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -613,6 +613,7 @@ static void arm1176_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->midr = 0x410fb767;
     cpu->reset_fpsid = 0x410120b5;
     cpu->mvfr0 = 0x11111111;
@@ -699,6 +700,7 @@ static void cortex_a8_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->midr = 0x410fc080;
     cpu->reset_fpsid = 0x410330c0;
     cpu->mvfr0 = 0x11110222;
@@ -766,6 +768,7 @@ static void cortex_a9_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     /* Note that A9 supports the MP extensions even for
      * A9UP and single-core A9MP (which are both different
      * and valid configurations; we don't model A9UP).
@@ -833,6 +836,7 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_LPAE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;
     cpu->reset_fpsid = 0x410430f0;
-- 
1.8.3.2

      parent reply	other threads:[~2014-11-05 23:24 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-05 23:22 [Qemu-devel] [PATCH v9 00/26] target-arm: add Security Extensions for CPUs Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 01/26] target-arm: extend async excp masking Greg Bellows
2014-11-05 23:37   ` Peter Maydell
2014-11-06  1:29     ` Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 02/26] target-arm: add async excp target_el function Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 03/26] target-arm: add banked register accessors Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 04/26] target-arm: add non-secure Translation Block flag Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 05/26] target-arm: add CPREG secure state support Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 06/26] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 07/26] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 08/26] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 10/26] target-arm: add NSACR register Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 11/26] target-arm: add SDER definition Greg Bellows
2014-11-05 23:22 ` [Qemu-devel] [PATCH v9 12/26] target-arm: add MVBAR support Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 15/26] target-arm: make CSSELR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 16/26] target-arm: make TTBR0/1 banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 17/26] target-arm: make TTBCR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 18/26] target-arm: make DACR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 19/26] target-arm: make IFSR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 20/26] target-arm: make DFSR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 21/26] target-arm: make IFAR/DFAR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 22/26] target-arm: make PAR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 23/26] target-arm: make VBAR banked Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 24/26] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-11-05 23:23 ` [Qemu-devel] [PATCH v9 25/26] target-arm: make MAIR0/1 banked Greg Bellows
2014-11-05 23:23 ` Greg Bellows [this message]

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