From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vs-0004yz-H0 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:24:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vn-0004lG-4U for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:24:08 -0500 Received: from mail-pd0-f178.google.com ([209.85.192.178]:39137) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vm-0004lA-Vo for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:24:03 -0500 Received: by mail-pd0-f178.google.com with SMTP id fp1so1696205pdb.9 for ; Wed, 05 Nov 2014 15:24:02 -0800 (PST) From: Greg Bellows Date: Wed, 5 Nov 2014 17:23:13 -0600 Message-Id: <1415229793-3278-27-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v9 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Cc: greg.bellows@linaro.org From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 53b311a..4c36e2e 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -613,6 +613,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -699,6 +700,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -766,6 +768,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -833,6 +836,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0; -- 1.8.3.2