From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36538) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLP-0001Ry-Li for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLI-0003tc-65 for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:31 -0500 Received: from mail-pa0-f47.google.com ([209.85.220.47]:46731) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLI-0003tX-0Y for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:24 -0500 Received: by mail-pa0-f47.google.com with SMTP id kx10so1477152pab.34 for ; Thu, 06 Nov 2014 07:51:23 -0800 (PST) From: Greg Bellows Date: Thu, 6 Nov 2014 09:50:47 -0600 Message-Id: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v10 00/26] target-arm: add Security Extensions for CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Cc: greg.bellows@linaro.org Version 10 of the ARM processor security extension (TrustZone) support. This patchset includes changes to support the processor security extensions on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32. This is a rebase of v9 to a more recent master as well as a fix for an overlooked bug in patch 12 that broke AA64. Fabian Aggeler (19): target-arm: add banked register accessors target-arm: add CPREG secure state support target-arm: insert AArch32 cpregs twice into hashtable target-arm: move AArch32 SCR into security reglist target-arm: implement IRQ/FIQ routing to Monitor mode target-arm: add NSACR register target-arm: add MVBAR support target-arm: add SCTLR_EL3 and make SCTLR banked target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI target-arm: make CSSELR banked target-arm: make TTBR0/1 banked target-arm: make TTBCR banked target-arm: make DACR banked target-arm: make IFSR banked target-arm: make DFSR banked target-arm: make IFAR/DFAR banked target-arm: make PAR banked target-arm: make c13 cp regs banked (FCSEIDR, ...) target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows (6): target-arm: extend async excp masking target-arm: add async excp target_el function target-arm: add secure state bit to CPREG hash target-arm: add SDER definition target-arm: make VBAR banked target-arm: make MAIR0/1 banked Sergey Fedorov (1): target-arm: add non-secure Translation Block flag hw/arm/pxa2xx.c | 6 +- linux-user/aarch64/target_cpu.h | 2 +- linux-user/arm/target_cpu.h | 2 +- linux-user/main.c | 2 +- target-arm/cpu.c | 14 +- target-arm/cpu.h | 364 ++++++++++++++++++--- target-arm/helper.c | 682 ++++++++++++++++++++++++++++++---------- target-arm/internals.h | 6 +- target-arm/op_helper.c | 4 +- target-arm/translate.c | 15 +- target-arm/translate.h | 1 + 11 files changed, 868 insertions(+), 230 deletions(-) -- 1.8.3.2