From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLl-0001sp-Ii for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLf-0004Ia-IC for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:53 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:48398) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLf-0004IU-Db for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:47 -0500 Received: by mail-pa0-f49.google.com with SMTP id lj1so1477975pab.22 for ; Thu, 06 Nov 2014 07:51:47 -0800 (PST) From: Greg Bellows Date: Thu, 6 Nov 2014 09:50:58 -0600 Message-Id: <1415289073-14681-12-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v10 11/26] target-arm: add SDER definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Cc: greg.bellows@linaro.org Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Fixed declaration order of the SDER register components v7 -> v8 - Added SDER32_EL3 register definition - Changed sder name from c1_sder to sder - Changed sder from uint32_t to uint64_t. --- target-arm/cpu.h | 1 + target-arm/helper.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 97f952c..7a860e6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 016cf39..cb15ad4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.sder) }, + { .name = "SDER", + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, .access = PL3_W | PL1_R, .resetvalue = 0, -- 1.8.3.2