From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, serge.fdrv@gmail.com,
edgar.iglesias@gmail.com, aggelerf@ethz.ch,
peter.maydell@linaro.org
Cc: greg.bellows@linaro.org
Subject: [Qemu-devel] [PATCH v10 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions
Date: Thu, 6 Nov 2014 09:51:13 -0600 [thread overview]
Message-ID: <1415289073-14681-27-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org>
From: Fabian Aggeler <aggelerf@ethz.ch>
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
target-arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d3db279..1871865 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -640,6 +640,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
@@ -728,6 +729,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
@@ -795,6 +797,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
@@ -862,6 +865,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
--
1.8.3.2
prev parent reply other threads:[~2014-11-06 15:52 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-06 15:50 [Qemu-devel] [PATCH v10 00/26] target-arm: add Security Extensions for CPUs Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 01/26] target-arm: extend async excp masking Greg Bellows
2014-11-17 14:46 ` Peter Maydell
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 02/26] target-arm: add async excp target_el function Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 03/26] target-arm: add banked register accessors Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 04/26] target-arm: add non-secure Translation Block flag Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 05/26] target-arm: add CPREG secure state support Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 06/26] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-11-17 14:59 ` Peter Maydell
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-11-17 15:00 ` Peter Maydell
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 08/26] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 10/26] target-arm: add NSACR register Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 11/26] target-arm: add SDER definition Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 12/26] target-arm: add MVBAR support Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-11-17 15:13 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-11-17 15:10 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 15/26] target-arm: make CSSELR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 16/26] target-arm: make TTBR0/1 banked Greg Bellows
2014-11-17 15:22 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 17/26] target-arm: make TTBCR banked Greg Bellows
2014-11-17 15:34 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 18/26] target-arm: make DACR banked Greg Bellows
2014-11-17 15:19 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 19/26] target-arm: make IFSR banked Greg Bellows
2014-11-17 15:16 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 20/26] target-arm: make DFSR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 21/26] target-arm: make IFAR/DFAR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 22/26] target-arm: make PAR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 23/26] target-arm: make VBAR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 24/26] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-11-17 15:25 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 25/26] target-arm: make MAIR0/1 banked Greg Bellows
2014-11-06 15:51 ` Greg Bellows [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1415289073-14681-27-git-send-email-greg.bellows@linaro.org \
--to=greg.bellows@linaro.org \
--cc=aggelerf@ethz.ch \
--cc=edgar.iglesias@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=serge.fdrv@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).