From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmmqA-0003WV-NL for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xmmq6-0006e9-7S for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:50 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:35835) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xmmq6-0006e1-1J for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:46 -0500 From: Leon Alrae Date: Fri, 7 Nov 2014 16:56:05 +0000 Message-ID: <1415379369-16877-4-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> References: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 3/7] mips: Add macros for CP0.Config3 and CP0.Config4 bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Maciej W. Rozycki" From: "Maciej W. Rozycki" Define macros for CP0.Config3 and CP0.Config4 bits. These used to be exhaustive as at MIPS32r3, but more bits may have been added since. Signed-off-by: Maciej W. Rozycki Signed-off-by: Leon Alrae --- target-mips/cpu.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index d21da8e..c01bbda 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -424,17 +424,25 @@ struct CPUMIPSState { #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_BPG 30 +#define CP0C3_CMCGR 29 #define CP0C3_MSAP 28 #define CP0C3_BP 27 #define CP0C3_BI 26 +#define CP0C3_IPLW 21 +#define CP0C3_MMAR 18 +#define CP0C3_MCU 17 #define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ISA 14 #define CP0C3_ULRI 13 #define CP0C3_RXI 12 +#define CP0C3_DSP2P 11 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 #define CP0C3_VInt 5 #define CP0C3_SP 4 +#define CP0C3_CDMM 3 #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 @@ -443,6 +451,11 @@ struct CPUMIPSState { #define CP0C4_M 31 #define CP0C4_IE 29 #define CP0C4_KScrExist 16 +#define CP0C4_MMUExtDef 14 +#define CP0C4_FTLBPageSize 8 +#define CP0C4_FTLBWays 4 +#define CP0C4_FTLBSets 0 +#define CP0C4_MMUSizeExt 0 uint32_t CP0_Config5; uint32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31 -- 2.1.0