From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59512) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmmqE-0003dn-IE for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xmmq8-0006ex-Kx for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:54 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:42971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xmmq8-0006et-Ee for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:48 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 2E6EDB893C66A for ; Fri, 7 Nov 2014 16:56:44 +0000 (GMT) From: Leon Alrae Date: Fri, 7 Nov 2014 16:56:09 +0000 Message-ID: <1415379369-16877-8-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> References: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Yongbok Kim From: Yongbok Kim Avoid to allocate different TCG registers for the FPU registers that are mapped on the MSA vectore registers. Signed-off-by: Yongbok Kim Reviewed-by: Richard Henderson Signed-off-by: Leon Alrae --- target-mips/translate.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 0bea3c4..f0b8e6f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19285,14 +19285,12 @@ void mips_tcg_init(void) regnames[i]); for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i]); - fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]); - } - - for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]); + /* The scalar floating-point unit (FPU) registers are mapped on + * the MSA vector registers. */ + fpu_f64[i] = msa_wr_d[i * 2]; off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]); -- 2.1.0