From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XoCM8-00036n-TX for qemu-devel@nongnu.org; Tue, 11 Nov 2014 09:23:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XoCM2-0007bN-St for qemu-devel@nongnu.org; Tue, 11 Nov 2014 09:23:40 -0500 Received: from mail-wi0-x229.google.com ([2a00:1450:400c:c05::229]:35914) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XoCM2-0007bG-LY for qemu-devel@nongnu.org; Tue, 11 Nov 2014 09:23:34 -0500 Received: by mail-wi0-f169.google.com with SMTP id n3so1940257wiv.0 for ; Tue, 11 Nov 2014 06:23:34 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 11 Nov 2014 15:23:21 +0100 Message-Id: <1415715801-30782-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1415715801-30782-1-git-send-email-pbonzini@redhat.com> References: <1415715801-30782-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 3/3] apic: fix incorrect handling of ExtINT interrupts wrt processor priority List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rbilson@qnx.com This fixes another failure with ExtINT, demonstrated by QNX. The failure mode is as follows: - IPI sent to cpu 0 (bit set in APIC irr) - IPI accepted by cpu 0 (bit cleared in irr, set in isr) - IPI sent to cpu 0 (bit set in both irr and isr) - PIC interrupt sent to cpu 0 The PIC interrupt causes CPU_INTERRUPT_HARD to be set, but apic_irq_pending observes that the highest pending APIC interrupt priority (the IPI) is the same as the processor priority (since the IPI is still being handled), so apic_get_interrupt returns a spurious interrupt rather than the pending PIC interrupt. The result is an endless sequence of spurious interrupts, since nothing will clear CPU_INTERRUPT_HARD. Instead, ExtINT interrupts should have ignored the processor priority. Calling apic_check_pic early in apic_get_interrupt ensures that apic_deliver_pic_intr is called instead of delivering the spurious interrupt. apic_deliver_pic_intr then clears CPU_INTERRUPT_HARD if needed. Reported-by: Richard Bilson Signed-off-by: Paolo Bonzini --- hw/intc/apic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 6ec5861..0f97b47 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -571,7 +571,10 @@ int apic_get_interrupt(DeviceState *dev) apic_sync_vapic(s, SYNC_FROM_VAPIC); intno = apic_irq_pending(s); - if (intno == 0) { + /* if there is an interrupt from the 8259, let the caller handle + * that first since ExtINT interrupts ignore the priority. + */ + if (intno == 0 || apic_check_pic(s)) { apic_sync_vapic(s, SYNC_TO_VAPIC); return -1; } else if (intno < 0) { @@ -582,9 +585,6 @@ int apic_get_interrupt(DeviceState *dev) apic_set_bit(s->isr, intno); apic_sync_vapic(s, SYNC_TO_VAPIC); - /* re-inject if there is still a pending PIC interrupt */ - apic_check_pic(s); - apic_update_irq(s); return intno; -- 2.1.0