From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46157) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xox0Y-0007WG-96 for qemu-devel@nongnu.org; Thu, 13 Nov 2014 11:12:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xox0S-0001WW-T8 for qemu-devel@nongnu.org; Thu, 13 Nov 2014 11:12:30 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:46684) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xox0S-0001WQ-MC for qemu-devel@nongnu.org; Thu, 13 Nov 2014 11:12:24 -0500 From: Bastian Koppelmann Date: Thu, 13 Nov 2014 17:12:43 +0000 Message-Id: <1415898767-20461-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v2 0/4] Add TriCore RCPW, RCRR, RCRW, RLC and RCR instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Hi, this patch depends on the previous TriCore patches (https://patchwork.ozlabs.org/patch/405459/) and will hopefully end up in 2.3 QEMU. Other than adding the RCPW, RCRR, RCRW, RLC and RCR instructions, it cleans up how ISA versions in the feature bitmask are handled, to simplify the checks, when instructions are available. Thanks, Bastian v1 -> v2: - Fixed obvious style errors, given by checkpatch. Bastian Koppelmann (4): target-tricore: Make TRICORE_FEATURES implying others. target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format target-tricore: Add instructions of RLC opcode format target-tricore: Add instructions of RCR opcode format target-tricore/cpu.c | 9 + target-tricore/csfr.def | 124 +++++++ target-tricore/helper.h | 11 + target-tricore/op_helper.c | 203 +++++++++++ target-tricore/translate.c | 744 ++++++++++++++++++++++++++++++++++++++- target-tricore/tricore-opcodes.h | 4 +- 6 files changed, 1088 insertions(+), 7 deletions(-) create mode 100644 target-tricore/csfr.def -- 2.1.3