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From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, agraf@suse.de
Subject: [Qemu-devel] [PATCH] target-ppc: Altivec's mtvscr Decodes Wrong Register
Date: Fri, 14 Nov 2014 14:01:41 -0600	[thread overview]
Message-ID: <1415995301-13402-1-git-send-email-tommusta@gmail.com> (raw)

The Move to Vector Status and Control Register (mtvscr) instruction
uses VRB as the source register.  Fix the code generator to correctly
decode the VRB field.  That is, use "rB(ctx->opcode)" instead of
"rD(ctx->opcode)".

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
 target-ppc/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 910ce56..d381632 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6848,7 +6848,7 @@ static void gen_mtvscr(DisasContext *ctx)
         gen_exception(ctx, POWERPC_EXCP_VPU);
         return;
     }
-    p = gen_avr_ptr(rD(ctx->opcode));
+    p = gen_avr_ptr(rB(ctx->opcode));
     gen_helper_mtvscr(cpu_env, p);
     tcg_temp_free_ptr(p);
 }
-- 
1.7.1

             reply	other threads:[~2014-11-14 20:02 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-14 20:01 Tom Musta [this message]
2014-11-15 12:37 ` [Qemu-devel] [PATCH] target-ppc: Altivec's mtvscr Decodes Wrong Register Alexander Graf

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