From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTX-0001V4-UT for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTT-0007BB-67 for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:27 -0500 Received: from mail-pd0-f176.google.com ([209.85.192.176]:61505) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTT-0007B5-1f for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:23 -0500 Received: by mail-pd0-f176.google.com with SMTP id y10so2173797pdj.21 for ; Mon, 17 Nov 2014 08:48:22 -0800 (PST) From: Greg Bellows Date: Mon, 17 Nov 2014 10:47:41 -0600 Message-Id: <1416242878-876-10-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v11 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Cc: greg.bellows@linaro.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6c4b467..8651bbc 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4233,12 +4233,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: -- 1.8.3.2