[Qemu-devel] [PULL 2.2 0/3] ppc patch queue 2014-11-20

[Qemu-devel] [PULL 2.2 0/3] ppc patch queue 2014-11-20

[Alexander Graf]

Hi Peter,

This is my current patch queue for ppc.  Please pull.

Alex


The following changes since commit af3ff19b48f0bbf3a8bd35c47460358e8c6ae5e5:

  Update version for v2.2.0-rc2 release (2014-11-18 18:00:58 +0000)

are available in the git repository at:

  git://github.com/agraf/qemu.git tags/signed-ppc-for-upstream

for you to fetch changes up to 76cb6584196b6f35d6e9b5124974d3eba643f772:

  target-ppc: Altivec's mtvscr Decodes Wrong Register (2014-11-20 14:52:01 +0100)

----------------------------------------------------------------
Patch queue for ppc - 2014-11-20

Hopefully the last few fixups for 2.2:

  - KVM memory slot fix (should usually only occur on PPC)
  - e300 fix
  - Altivec mtvscr instruction fix

----------------------------------------------------------------
Alexander Graf (1):
      kvm: Fix memory slot page alignment logic

Fabien Chouteau (1):
      target-ppc: Fix breakpoint registers for e300

Tom Musta (1):
      target-ppc: Altivec's mtvscr Decodes Wrong Register

 kvm-all.c                   |  6 ++++--
 target-ppc/translate.c      |  2 +-
 target-ppc/translate_init.c | 52 ++++++++++++++++++++++-----------------------
 3 files changed, 31 insertions(+), 29 deletions(-)

[Qemu-devel] [PULL 2.2 1/3] target-ppc: Fix breakpoint registers for e300

[Alexander Graf]

From: Fabien Chouteau <chouteau@adacore.com>

In the previous patch, the registers were added to init_proc_G2LE
instead of init_proc_e300.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate_init.c | 52 ++++++++++++++++++++++-----------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 20d58c0..1fece7b 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4374,32 +4374,6 @@ static void init_proc_G2LE (CPUPPCState *env)
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_generic,
                  0x00000000);
-    /* Breakpoints */
-    /* XXX : not implemented */
-    spr_register(env, SPR_DABR, "DABR",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_DABR2, "DABR2",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_IABR2, "IABR2",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_IBCR, "IBCR",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_DBCR, "DBCR",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
 
     /* Memory management */
     gen_low_BATs(env);
@@ -4628,6 +4602,32 @@ static void init_proc_e300 (CPUPPCState *env)
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_generic,
                  0x00000000);
+    /* Breakpoints */
+    /* XXX : not implemented */
+    spr_register(env, SPR_DABR, "DABR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_DABR2, "DABR2",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_IABR2, "IABR2",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_IBCR, "IBCR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_DBCR, "DBCR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
     /* Memory management */
     gen_low_BATs(env);
     gen_high_BATs(env);
-- 
1.8.1.4

[Qemu-devel] [PULL 2.2 2/3] kvm: Fix memory slot page alignment logic

[Alexander Graf]

Memory slots have to be page aligned to get entered into KVM. There
is existing logic that tries to ensure that we pad memory slots that
are not page aligned to the biggest region that would still fit in the
alignment requirements.

Unfortunately, that logic is broken. It tries to calculate the start
offset based on the region size.

Fix up the logic to do the thing it was intended to do and document it
properly in the comment above it.

With this patch applied, I can successfully run an e500 guest with more
than 3GB RAM (at which point RAM starts overlapping subpage memory regions).

Cc: qemu-stable@nongnu.org
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 kvm-all.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/kvm-all.c b/kvm-all.c
index 44a5e72..596e7ce 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -634,8 +634,10 @@ static void kvm_set_phys_mem(MemoryRegionSection *section, bool add)
     unsigned delta;
 
     /* kvm works in page size chunks, but the function may be called
-       with sub-page size and unaligned start address. */
-    delta = TARGET_PAGE_ALIGN(size) - size;
+       with sub-page size and unaligned start address. Pad the start
+       address to next and truncate size to previous page boundary. */
+    delta = (TARGET_PAGE_SIZE - (start_addr & ~TARGET_PAGE_MASK));
+    delta &= ~TARGET_PAGE_MASK;
     if (delta > size) {
         return;
     }
-- 
1.8.1.4

[Qemu-devel] [PULL 2.2 3/3] target-ppc: Altivec's mtvscr Decodes Wrong Register

[Alexander Graf]

From: Tom Musta <tommusta@gmail.com>

The Move to Vector Status and Control Register (mtvscr) instruction
uses VRB as the source register.  Fix the code generator to correctly
decode the VRB field.  That is, use "rB(ctx->opcode)" instead of
"rD(ctx->opcode)".

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 910ce56..d381632 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6848,7 +6848,7 @@ static void gen_mtvscr(DisasContext *ctx)
         gen_exception(ctx, POWERPC_EXCP_VPU);
         return;
     }
-    p = gen_avr_ptr(rD(ctx->opcode));
+    p = gen_avr_ptr(rB(ctx->opcode));
     gen_helper_mtvscr(cpu_env, p);
     tcg_temp_free_ptr(p);
 }
-- 
1.8.1.4

Re: [Qemu-devel] [PULL 2.2 0/3] ppc patch queue 2014-11-20

[Peter Maydell]

On 20 November 2014 13:55, Alexander Graf <agraf@suse.de> wrote:
> Hi Peter,
>
> This is my current patch queue for ppc.  Please pull.
>
> Alex
>
>
> The following changes since commit af3ff19b48f0bbf3a8bd35c47460358e8c6ae5e5:
>
>   Update version for v2.2.0-rc2 release (2014-11-18 18:00:58 +0000)
>
> are available in the git repository at:
>
>   git://github.com/agraf/qemu.git tags/signed-ppc-for-upstream
>
> for you to fetch changes up to 76cb6584196b6f35d6e9b5124974d3eba643f772:
>
>   target-ppc: Altivec's mtvscr Decodes Wrong Register (2014-11-20 14:52:01 +0100)
>
> ----------------------------------------------------------------
> Patch queue for ppc - 2014-11-20
>
> Hopefully the last few fixups for 2.2:
>
>   - KVM memory slot fix (should usually only occur on PPC)
>   - e300 fix
>   - Altivec mtvscr instruction fix
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM