From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 1/3] apic: avoid getting out of halted state on masked PIC interrupts
Date: Mon, 24 Nov 2014 14:40:47 +0100 [thread overview]
Message-ID: <1416836449-2599-2-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1416836449-2599-1-git-send-email-pbonzini@redhat.com>
After the next patch, if a masked PIC interrupts causes CPU_INTERRUPT_POLL
to be set, the CPU will spuriously get out of halted state. While this
is technically valid, we should avoid that.
Make CPU_INTERRUPT_POLL run apic_update_irq in the right thread and then
look at CPU_INTERRUPT_HARD. If CPU_INTERRUPT_HARD does not get set,
do not report the CPU as having work.
Also move the handling of software-disabled APIC from apic_update_irq
to apic_irq_pending, and always trigger CPU_INTERRUPT_POLL. This will
be important once we will add a case that resets CPU_INTERRUPT_HARD
from apic_update_irq. We want to run it even if we go through
CPU_INTERRUPT_POLL, and even if the local APIC is software disabled.
Reported-by: Richard Bilson <rbilson@qnx.com>
Tested-by: Richard Bilson <rbilson@qnx.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/intc/apic.c | 8 +++++---
target-i386/cpu.c | 10 ++++++++--
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 03ff9e9..0653409 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -349,6 +349,11 @@ static int apic_get_arb_pri(APICCommonState *s)
static int apic_irq_pending(APICCommonState *s)
{
int irrv, ppr;
+
+ if (!(s->spurious_vec & APIC_SV_ENABLE)) {
+ return 0;
+ }
+
irrv = get_highest_priority_int(s->irr);
if (irrv < 0) {
return 0;
@@ -366,9 +371,6 @@ static void apic_update_irq(APICCommonState *s)
{
CPUState *cpu;
- if (!(s->spurious_vec & APIC_SV_ENABLE)) {
- return;
- }
cpu = CPU(s->cpu);
if (!qemu_cpu_is_self(cpu)) {
cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 3f13dfe..e9df33e 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2912,8 +2912,14 @@ static bool x86_cpu_has_work(CPUState *cs)
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_POLL)) &&
+#if !defined(CONFIG_USER_ONLY)
+ if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
+ apic_poll_irq(cpu->apic_state);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
+ }
+#endif
+
+ return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
(cs->interrupt_request & (CPU_INTERRUPT_NMI |
CPU_INTERRUPT_INIT |
--
1.8.3.1
next prev parent reply other threads:[~2014-11-24 13:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-24 13:40 [Qemu-devel] [PULL for-2.2 0/3] APIC fixes for 2014-11-24 Paolo Bonzini
2014-11-24 13:40 ` Paolo Bonzini [this message]
2014-11-24 13:40 ` [Qemu-devel] [PULL 2/3] apic: fix loss of IPI due to masked ExtINT Paolo Bonzini
2014-11-24 13:40 ` [Qemu-devel] [PULL 3/3] apic: fix incorrect handling of ExtINT interrupts wrt processor priority Paolo Bonzini
2014-11-24 15:01 ` [Qemu-devel] [PULL for-2.2 0/3] APIC fixes for 2014-11-24 Peter Maydell
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