From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xstt3-0000Ln-Ku for qemu-devel@nongnu.org; Mon, 24 Nov 2014 08:41:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xstsw-0008Gk-0k for qemu-devel@nongnu.org; Mon, 24 Nov 2014 08:41:05 -0500 Received: from mail-wg0-x22c.google.com ([2a00:1450:400c:c00::22c]:47868) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xstsv-0008GY-Pl for qemu-devel@nongnu.org; Mon, 24 Nov 2014 08:40:57 -0500 Received: by mail-wg0-f44.google.com with SMTP id b13so12316932wgh.31 for ; Mon, 24 Nov 2014 05:40:57 -0800 (PST) Received: from playground.station (net-93-146-133-240.cust.vodafonedsl.it. [93.146.133.240]) by mx.google.com with ESMTPSA id j8sm12093033wib.10.2014.11.24.05.40.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Nov 2014 05:40:56 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 24 Nov 2014 14:40:47 +0100 Message-Id: <1416836449-2599-2-git-send-email-pbonzini@redhat.com> In-Reply-To: <1416836449-2599-1-git-send-email-pbonzini@redhat.com> References: <1416836449-2599-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 1/3] apic: avoid getting out of halted state on masked PIC interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org After the next patch, if a masked PIC interrupts causes CPU_INTERRUPT_POLL to be set, the CPU will spuriously get out of halted state. While this is technically valid, we should avoid that. Make CPU_INTERRUPT_POLL run apic_update_irq in the right thread and then look at CPU_INTERRUPT_HARD. If CPU_INTERRUPT_HARD does not get set, do not report the CPU as having work. Also move the handling of software-disabled APIC from apic_update_irq to apic_irq_pending, and always trigger CPU_INTERRUPT_POLL. This will be important once we will add a case that resets CPU_INTERRUPT_HARD from apic_update_irq. We want to run it even if we go through CPU_INTERRUPT_POLL, and even if the local APIC is software disabled. Reported-by: Richard Bilson Tested-by: Richard Bilson Signed-off-by: Paolo Bonzini --- hw/intc/apic.c | 8 +++++--- target-i386/cpu.c | 10 ++++++++-- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 03ff9e9..0653409 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -349,6 +349,11 @@ static int apic_get_arb_pri(APICCommonState *s) static int apic_irq_pending(APICCommonState *s) { int irrv, ppr; + + if (!(s->spurious_vec & APIC_SV_ENABLE)) { + return 0; + } + irrv = get_highest_priority_int(s->irr); if (irrv < 0) { return 0; @@ -366,9 +371,6 @@ static void apic_update_irq(APICCommonState *s) { CPUState *cpu; - if (!(s->spurious_vec & APIC_SV_ENABLE)) { - return; - } cpu = CPU(s->cpu); if (!qemu_cpu_is_self(cpu)) { cpu_interrupt(cpu, CPU_INTERRUPT_POLL); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 3f13dfe..e9df33e 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2912,8 +2912,14 @@ static bool x86_cpu_has_work(CPUState *cs) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; - return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_POLL)) && +#if !defined(CONFIG_USER_ONLY) + if (cs->interrupt_request & CPU_INTERRUPT_POLL) { + apic_poll_irq(cpu->apic_state); + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); + } +#endif + + return ((cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || (cs->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_INIT | -- 1.8.3.1