qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, serge.fdrv@gmail.com,
	edgar.iglesias@gmail.com, aggelerf@ethz.ch,
	peter.maydell@linaro.org
Cc: Greg Bellows <greg.bellows@linaro.org>
Subject: [Qemu-devel] [PATCH 13/13] target-arm: add cpu feature EL3 to CPUs with Security Extensions
Date: Wed,  3 Dec 2014 14:06:07 -0600	[thread overview]
Message-ID: <1417637167-20640-14-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1417637167-20640-1-git-send-email-greg.bellows@linaro.org>

From: Fabian Aggeler <aggelerf@ethz.ch>

Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
 target-arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 0e660f9..9e8d40c 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -669,6 +669,7 @@ static void arm1176_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->midr = 0x410fb767;
     cpu->reset_fpsid = 0x410120b5;
     cpu->mvfr0 = 0x11111111;
@@ -757,6 +758,7 @@ static void cortex_a8_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->midr = 0x410fc080;
     cpu->reset_fpsid = 0x410330c0;
     cpu->mvfr0 = 0x11110222;
@@ -824,6 +826,7 @@ static void cortex_a9_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     /* Note that A9 supports the MP extensions even for
      * A9UP and single-core A9MP (which are both different
      * and valid configurations; we don't model A9UP).
@@ -891,6 +894,7 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_LPAE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;
     cpu->reset_fpsid = 0x410430f0;
-- 
1.8.3.2

      parent reply	other threads:[~2014-12-03 20:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-03 20:05 [Qemu-devel] [PATCH 00/13] target-arm: Add CPU security extension enablement Greg Bellows
2014-12-03 20:05 ` [Qemu-devel] [PATCH 01/13] target-arm: Add vexpress class and machine types Greg Bellows
2014-12-05 15:16   ` Peter Maydell
2014-12-05 19:02     ` Marcel Apfelbaum
2014-12-05 20:04       ` Greg Bellows
2014-12-03 20:05 ` [Qemu-devel] [PATCH 02/13] target-arm: Add vexpress a9 & a15 machine objects Greg Bellows
2014-12-03 20:05 ` [Qemu-devel] [PATCH 03/13] target-arm: Switch to common vexpress machine init Greg Bellows
2014-12-03 20:05 ` [Qemu-devel] [PATCH 04/13] target-arm: Add secure qemu machine option Greg Bellows
2014-12-05 15:18   ` Peter Maydell
2014-12-05 15:33     ` Greg Bellows
2014-12-05 15:39       ` Peter Maydell
2014-12-05 19:40         ` Marcel Apfelbaum
2014-12-05 20:40           ` Greg Bellows
2014-12-05 22:44             ` Marcel Apfelbaum
2014-12-05 22:53               ` Greg Bellows
2014-12-03 20:05 ` [Qemu-devel] [PATCH 05/13] target-arm: Add vexpress machine secure property Greg Bellows
2014-12-05 15:20   ` Peter Maydell
2014-12-03 20:06 ` [Qemu-devel] [PATCH 06/13] target-arm: Change vexpress daughterboard init arg Greg Bellows
2014-12-03 20:06 ` [Qemu-devel] [PATCH 07/13] target-arm: Add virt class and machine types Greg Bellows
2014-12-03 20:06 ` [Qemu-devel] [PATCH 08/13] target-arm: Add virt machine secure property Greg Bellows
2014-12-03 20:06 ` [Qemu-devel] [PATCH 09/13] target-arm: Add feature unset function Greg Bellows
2014-12-05 15:22   ` Peter Maydell
2014-12-03 20:06 ` [Qemu-devel] [PATCH 10/13] target-arm: Add ARMCPU secure property Greg Bellows
2014-12-05 15:26   ` Peter Maydell
2014-12-05 19:41     ` Greg Bellows
2014-12-03 20:06 ` [Qemu-devel] [PATCH 11/13] target-arm: Set CPU secure prop during VE init Greg Bellows
2014-12-03 20:06 ` [Qemu-devel] [PATCH 12/13] target-arm: Set CPU secure prop during virt init Greg Bellows
2014-12-03 20:06 ` Greg Bellows [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1417637167-20640-14-git-send-email-greg.bellows@linaro.org \
    --to=greg.bellows@linaro.org \
    --cc=aggelerf@ethz.ch \
    --cc=edgar.iglesias@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=serge.fdrv@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).