From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: pranavkumar@linaro.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Christoffer Dall" <christoffer.dall@linaro.org>,
patches@linaro.org
Subject: [Qemu-devel] [PATCH 2/2] target-arm: Support save/load for 64 bit CPUs
Date: Fri, 5 Dec 2014 14:11:23 +0000 [thread overview]
Message-ID: <1417788683-4038-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1417788683-4038-1-git-send-email-peter.maydell@linaro.org>
For migration to work on 64 bit CPUs, we need to include both
the 64-bit integer register file and the PSTATE. Everything
else is either stored in the same place as existing 32-bit CPU
state or handled by the generic sysreg mechanism.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
The pstate save/load is a little ugly and suggests that we
could perhaps benefit from unifying the state storage/access
for 64-bit pstate and 32-bit PSR; however Alex had a go at
that a while back and it turns out to be trickier than it
looks. This is a pragmatic fix which makes save/load work
(and the on-the-wire state is right, at least).
---
target-arm/machine.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 6437690..c29e7a2 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -127,6 +127,13 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
CPUARMState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
+ env->aarch64 = ((val & PSTATE_nRW) == 0);
+
+ if (is_a64(env)) {
+ pstate_write(env, val);
+ return 0;
+ }
+
/* Avoid mode switch when restoring CPSR */
env->uncached_cpsr = val & CPSR_M;
cpsr_write(env, val, 0xffffffff);
@@ -137,8 +144,15 @@ static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
+ uint32_t val;
+
+ if (is_a64(env)) {
+ val = pstate_read(env);
+ } else {
+ val = cpsr_read(env);
+ }
- qemu_put_be32(f, cpsr_read(env));
+ qemu_put_be32(f, val);
}
static const VMStateInfo vmstate_cpsr = {
@@ -222,12 +236,14 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
- .version_id = 21,
- .minimum_version_id = 21,
+ .version_id = 22,
+ .minimum_version_id = 22,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
+ VMSTATE_UINT64(env.pc, ARMCPU),
{
.name = "cpsr",
.version_id = 0,
--
1.9.1
next prev parent reply other threads:[~2014-12-05 14:15 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-05 14:11 [Qemu-devel] [PATCH 0/2] support migration/save/load on AArch64 CPUs Peter Maydell
2014-12-05 14:11 ` [Qemu-devel] [PATCH 1/2] target-arm/kvm: make reg sync code common between kvm32/64 Peter Maydell
2014-12-05 14:11 ` Peter Maydell [this message]
2014-12-09 11:07 ` [Qemu-devel] [PATCH 0/2] support migration/save/load on AArch64 CPUs Pranavkumar Sawargaonkar
2014-12-09 11:43 ` Peter Maydell
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