From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xwwvv-0007Vs-09 for qemu-devel@nongnu.org; Fri, 05 Dec 2014 12:44:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xwwvl-0003iz-Sz for qemu-devel@nongnu.org; Fri, 05 Dec 2014 12:44:46 -0500 Received: from mail-wg0-x234.google.com ([2a00:1450:400c:c00::234]:33980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xwwvl-0003iY-I8 for qemu-devel@nongnu.org; Fri, 05 Dec 2014 12:44:37 -0500 Received: by mail-wg0-f52.google.com with SMTP id a1so1518232wgh.11 for ; Fri, 05 Dec 2014 09:44:37 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 5 Dec 2014 18:44:24 +0100 Message-Id: <1417801466-23485-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1417801466-23485-1-git-send-email-pbonzini@redhat.com> References: <1417801466-23485-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: ehabkost@redhat.com vm86 mode extensions date back to the 486. All models should have them. Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 15 +++++++++++++++ hw/i386/pc_q35.c | 15 +++++++++++++++ target-i386/cpu.c | 30 +++++++++++++++--------------- 3 files changed, 45 insertions(+), 15 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5ad23d0..3f1524e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -305,6 +305,21 @@ static void pc_init_pci(MachineState *machine) static void pc_compat_2_2(MachineState *machine) { + x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 1ff3828..bec234a 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -284,6 +284,21 @@ static void pc_q35_init(MachineState *machine) static void pc_compat_2_2(MachineState *machine) { + x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index ef7d71c..136c457 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -760,9 +760,9 @@ static X86CPUDefinition builtin_x86_defs[] = { .family = 15, .model = 6, .stepping = 1, - /* Missing: CPUID_VME, CPUID_HT */ + /* Missing: CPUID_HT */ .features[FEAT_1_EDX] = - PPRO_FEATURES | + PPRO_FEATURES | CPUID_VME | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ @@ -802,7 +802,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - PPRO_FEATURES | + PPRO_FEATURES | CPUID_VME | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, .features[FEAT_1_ECX] = CPUID_EXT_SSE3, @@ -928,7 +928,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 15, .stepping = 3, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -950,7 +950,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 23, .stepping = 3, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -973,7 +973,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 26, .stepping = 3, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -996,7 +996,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 44, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1020,7 +1020,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 42, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1049,7 +1049,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 60, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1084,7 +1084,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 61, .stepping = 2, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1120,7 +1120,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1145,7 +1145,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1173,7 +1173,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1203,7 +1203,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 1, .stepping = 2, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1238,7 +1238,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 2, .stepping = 0, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | -- 1.8.3.1