From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xy7SL-0006Hy-EC for qemu-devel@nongnu.org; Mon, 08 Dec 2014 18:11:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xy7SF-00060G-LK for qemu-devel@nongnu.org; Mon, 08 Dec 2014 18:11:05 -0500 Received: from mail-qa0-f53.google.com ([209.85.216.53]:45938) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xy7SF-000609-HS for qemu-devel@nongnu.org; Mon, 08 Dec 2014 18:10:59 -0500 Received: by mail-qa0-f53.google.com with SMTP id bm13so4026368qab.40 for ; Mon, 08 Dec 2014 15:10:59 -0800 (PST) Received: from localhost (207-172-170-53.c3-0.avec-ubr1.nyr-avec.ny.cable.rcn.com. [207.172.170.53]) by mx.google.com with ESMTPSA id k9sm27756139qaj.7.2014.12.08.15.10.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Dec 2014 15:10:58 -0800 (PST) From: Kevin O'Connor Date: Mon, 8 Dec 2014 18:10:34 -0500 Message-Id: <1418080234-31694-6-git-send-email-kevin@koconnor.net> In-Reply-To: <1418080234-31694-1-git-send-email-kevin@koconnor.net> References: <1418080234-31694-1-git-send-email-kevin@koconnor.net> Subject: [Qemu-devel] [PATCHv3 5/5] sdhci: Set a default frequency clock List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The Linux SDHCI PCI driver will only register the device if there is a clock frequency set. So, set a default frequency of 52Mhz. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d22740b..15064d3 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -74,10 +74,10 @@ #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul /* Maximum clock frequency for SDclock in MHz * value in range 10-63 MHz, 0 - not defined */ -#define SDHC_CAPAB_BASECLKFREQ 0ul +#define SDHC_CAPAB_BASECLKFREQ 52ul #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ /* Timeout clock frequency 1-63, 0 - not defined */ -#define SDHC_CAPAB_TOCLKFREQ 0ul +#define SDHC_CAPAB_TOCLKFREQ 52ul /* Now check all parameters and calculate CAPABILITIES REGISTER value */ #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ -- 1.9.3