* [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation
@ 2014-12-09 14:18 Stefan Berger
2014-12-09 14:18 ` [Qemu-devel] [PATCH 1/5] tpm: Extend sts register to 32 bit Stefan Berger
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Stefan Berger @ 2014-12-09 14:18 UTC (permalink / raw)
To: qemu-devel; +Cc: PeterHuewe, Stefan Berger, mst
The following series of patches extends the TPM TIS implementation to
version 1.3. This will lead to a TIS version that supports TPM 2.
For this I would post relatively small patches afterwards.
Regards,
Stefan
Stefan Berger (5):
tpm: Extend sts register to 32 bit
tpm: Allow 32 & 16 bit accesses to the registers
tpm: Support for XFIFO register
tpm: Support for TIS selftest done flag
tpm: Support for capability flags of TIS 1.3
hw/tpm/tpm_int.h | 1 +
hw/tpm/tpm_passthrough.c | 37 ++++++++++--
hw/tpm/tpm_tis.c | 131 ++++++++++++++++++++++++++++++++++---------
hw/tpm/tpm_tis.h | 2 +-
include/sysemu/tpm_backend.h | 2 +-
5 files changed, 139 insertions(+), 34 deletions(-)
--
1.9.3
^ permalink raw reply [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH 1/5] tpm: Extend sts register to 32 bit 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger @ 2014-12-09 14:18 ` Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 2/5] tpm: Allow 32 & 16 bit accesses to the registers Stefan Berger ` (4 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:18 UTC (permalink / raw) To: qemu-devel; +Cc: PeterHuewe, Stefan Berger, mst More recent TIS specs extend the STS register to 32 bit. While we don't store the TIS interface state, yet, we can extend it without sideeffects. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> --- hw/tpm/tpm_tis.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/tpm/tpm_tis.h b/hw/tpm/tpm_tis.h index 1a0db23..db78d51 100644 --- a/hw/tpm/tpm_tis.h +++ b/hw/tpm/tpm_tis.h @@ -41,7 +41,7 @@ typedef enum { typedef struct TPMLocality { TPMTISState state; uint8_t access; - uint8_t sts; + uint32_t sts; uint32_t inte; uint32_t ints; -- 1.9.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 2/5] tpm: Allow 32 & 16 bit accesses to the registers 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 1/5] tpm: Extend sts register to 32 bit Stefan Berger @ 2014-12-09 14:18 ` Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 3/5] tpm: Support for XFIFO register Stefan Berger ` (3 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:18 UTC (permalink / raw) To: qemu-devel; +Cc: PeterHuewe, Stefan Berger, mst Improve the access to the registers with 32 and 16 bit reads and writes. Also enable access to a non-base register address, such as reads of the 2nd byte of a register. Map the FIFO byte access to any byte within its 4 byte register (following specs). Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> --- hw/tpm/tpm_tis.c | 60 ++++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index c0e7cd7..6170693 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -427,6 +427,7 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, uint32_t val = 0xffffffff; uint8_t locty = tpm_tis_locality_from_addr(addr); uint32_t avail; + uint8_t v; if (tpm_backend_had_startup_error(s->be_driver)) { return val; @@ -476,14 +477,26 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, break; case TPM_TIS_REG_DATA_FIFO: if (tis->active_locty == locty) { - switch (tis->loc[locty].state) { - case TPM_TIS_STATE_COMPLETION: - val = tpm_tis_data_read(s, locty); - break; - default: - val = TPM_TIS_NO_DATA_BYTE; - break; + if (size > 4 - (addr & 0x3)) { + /* prevent access beyond FIFO */ + size = 4 - (addr & 0x3); + } + val = 0; + shift = 0; + while (size > 0) { + switch (tis->loc[locty].state) { + case TPM_TIS_STATE_COMPLETION: + v = tpm_tis_data_read(s, locty); + break; + default: + v = TPM_TIS_NO_DATA_BYTE; + break; + } + val |= (v << shift); + shift += 8; + size--; } + shift = 0; /* no more adjustments */ } break; case TPM_TIS_REG_DID_VID: @@ -518,11 +531,13 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, { TPMState *s = opaque; TPMTISEmuState *tis = &s->s.tis; - uint16_t off = addr & 0xfff; + uint16_t off = addr & 0xffc; + uint8_t shift = (addr & 0x3) * 8; uint8_t locty = tpm_tis_locality_from_addr(addr); uint8_t active_locty, l; int c, set_new_locty = 1; uint16_t len; + uint32_t mask = (size == 1) ? 0xff : ((size == 2) ? 0xffff : ~0); DPRINTF("tpm_tis: write.%u(%08x) = %08x\n", size, (int)addr, (uint32_t)val); @@ -535,6 +550,15 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, return; } + val &= mask; + + if (shift) { + val <<= shift; + mask <<= shift; + } + + mask ^= 0xffffffff; + switch (off) { case TPM_TIS_REG_ACCESS: @@ -646,9 +670,10 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, break; } - tis->loc[locty].inte = (val & (TPM_TIS_INT_ENABLED | - TPM_TIS_INT_POLARITY_MASK | - TPM_TIS_INTERRUPTS_SUPPORTED)); + tis->loc[locty].inte &= mask; + tis->loc[locty].inte |= (val & (TPM_TIS_INT_ENABLED | + TPM_TIS_INT_POLARITY_MASK | + TPM_TIS_INTERRUPTS_SUPPORTED)); break; case TPM_TIS_REG_INT_VECTOR: /* hard wired -- ignore */ @@ -747,16 +772,25 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, tis->loc[locty].state == TPM_TIS_STATE_COMPLETION) { /* drop the byte */ } else { - DPRINTF("tpm_tis: Byte to send to TPM: %02x\n", (uint8_t)val); + DPRINTF("tpm_tis: Data to send to TPM: %08x (size=%d)\n", + val, size); if (tis->loc[locty].state == TPM_TIS_STATE_READY) { tis->loc[locty].state = TPM_TIS_STATE_RECEPTION; tis->loc[locty].sts = TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID; } - if ((tis->loc[locty].sts & TPM_TIS_STS_EXPECT)) { + val >>= shift; + if (size > 4 - (addr & 0x3)) { + /* prevent access beyond FIFO */ + size = 4 - (addr & 0x3); + } + + while ((tis->loc[locty].sts & TPM_TIS_STS_EXPECT) && size > 0) { if (tis->loc[locty].w_offset < tis->loc[locty].w_buffer.size) { tis->loc[locty].w_buffer. buffer[tis->loc[locty].w_offset++] = (uint8_t)val; + val >>= 8; + size--; } else { tis->loc[locty].sts = TPM_TIS_STS_VALID; } -- 1.9.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 3/5] tpm: Support for XFIFO register 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 1/5] tpm: Extend sts register to 32 bit Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 2/5] tpm: Allow 32 & 16 bit accesses to the registers Stefan Berger @ 2014-12-09 14:18 ` Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 4/5] tpm: Support for TIS selftest done flag Stefan Berger ` (2 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:18 UTC (permalink / raw) To: qemu-devel; +Cc: PeterHuewe, Stefan Berger, mst Support for the XFIFO register (range) of the TIS 1.3 specification. We support a range of 64 bytes. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> --- hw/tpm/tpm_tis.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index 6170693..a37c7ce 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -51,6 +51,8 @@ #define TPM_TIS_REG_INTF_CAPABILITY 0x14 #define TPM_TIS_REG_STS 0x18 #define TPM_TIS_REG_DATA_FIFO 0x24 +#define TPM_TIS_REG_DATA_XFIFO 0x80 +#define TPM_TIS_REG_DATA_XFIFO_END 0xbc #define TPM_TIS_REG_DID_VID 0xf00 #define TPM_TIS_REG_RID 0xf04 @@ -476,6 +478,7 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, } break; case TPM_TIS_REG_DATA_FIFO: + case TPM_TIS_REG_DATA_XFIFO ... TPM_TIS_REG_DATA_XFIFO_END: if (tis->active_locty == locty) { if (size > 4 - (addr & 0x3)) { /* prevent access beyond FIFO */ @@ -762,6 +765,7 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, } break; case TPM_TIS_REG_DATA_FIFO: + case TPM_TIS_REG_DATA_XFIFO ... TPM_TIS_REG_DATA_XFIFO_END: /* data fifo */ if (tis->active_locty != locty) { break; -- 1.9.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 4/5] tpm: Support for TIS selftest done flag 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger ` (2 preceding siblings ...) 2014-12-09 14:18 ` [Qemu-devel] [PATCH 3/5] tpm: Support for XFIFO register Stefan Berger @ 2014-12-09 14:18 ` Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 5/5] tpm: Support for capability flags of TIS 1.3 Stefan Berger 2014-12-09 14:35 ` [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Michael S. Tsirkin 5 siblings, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:18 UTC (permalink / raw) To: qemu-devel; +Cc: PeterHuewe, Stefan Berger, mst Extend the backend to check whether the TPM_ContinueSelfTest finished successfully and provide a flag to the TIS front-end if it successfully finished. The TIS then sets a flag in all localities in the STS register and keeps it until the next reset. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> --- hw/tpm/tpm_int.h | 1 + hw/tpm/tpm_passthrough.c | 37 ++++++++++++++++++++++++---- hw/tpm/tpm_tis.c | 58 ++++++++++++++++++++++++++++++++++---------- include/sysemu/tpm_backend.h | 2 +- 4 files changed, 79 insertions(+), 19 deletions(-) diff --git a/hw/tpm/tpm_int.h b/hw/tpm/tpm_int.h index 2f582ca..2b35fe2 100644 --- a/hw/tpm/tpm_int.h +++ b/hw/tpm/tpm_int.h @@ -62,6 +62,7 @@ struct tpm_resp_hdr { #define TPM_FAIL 9 +#define TPM_ORD_ContinueSelfTest 0x53 #define TPM_ORD_GetTicks 0xf1 #endif /* TPM_TPM_INT_H */ diff --git a/hw/tpm/tpm_passthrough.c b/hw/tpm/tpm_passthrough.c index 56e9e0f..29063cf 100644 --- a/hw/tpm/tpm_passthrough.c +++ b/hw/tpm/tpm_passthrough.c @@ -112,14 +112,31 @@ static void tpm_write_fatal_error_response(uint8_t *out, uint32_t out_len) } } +static bool tpm_passthrough_is_selftest(const uint8_t *in, uint32_t in_len) +{ + struct tpm_req_hdr *hdr = (struct tpm_req_hdr *)in; + + if (in_len >= sizeof(*hdr)) { + return (be32_to_cpu(hdr->ordinal) == TPM_ORD_ContinueSelfTest); + } + + return false; +} + static int tpm_passthrough_unix_tx_bufs(TPMPassthruState *tpm_pt, const uint8_t *in, uint32_t in_len, - uint8_t *out, uint32_t out_len) + uint8_t *out, uint32_t out_len, + bool *selftest_done) { int ret; + bool is_selftest; + const struct tpm_resp_hdr *hdr; tpm_pt->tpm_op_canceled = false; tpm_pt->tpm_executing = true; + *selftest_done = false; + + is_selftest = tpm_passthrough_is_selftest(in, in_len); ret = tpm_passthrough_unix_write(tpm_pt->tpm_fd, in, in_len); if (ret != in_len) { @@ -149,6 +166,11 @@ static int tpm_passthrough_unix_tx_bufs(TPMPassthruState *tpm_pt, "packet from TPM\n"); } + if (is_selftest && (ret >= sizeof(struct tpm_resp_hdr))) { + hdr = (struct tpm_resp_hdr *)out; + *selftest_done = (be32_to_cpu(hdr->errcode) == 0); + } + err_exit: if (ret < 0) { tpm_write_fatal_error_response(out, out_len); @@ -160,13 +182,15 @@ err_exit: } static int tpm_passthrough_unix_transfer(TPMPassthruState *tpm_pt, - const TPMLocality *locty_data) + const TPMLocality *locty_data, + bool *selftest_done) { return tpm_passthrough_unix_tx_bufs(tpm_pt, locty_data->w_buffer.buffer, locty_data->w_offset, locty_data->r_buffer.buffer, - locty_data->r_buffer.size); + locty_data->r_buffer.size, + selftest_done); } static void tpm_passthrough_worker_thread(gpointer data, @@ -175,16 +199,19 @@ static void tpm_passthrough_worker_thread(gpointer data, TPMPassthruThreadParams *thr_parms = user_data; TPMPassthruState *tpm_pt = TPM_PASSTHROUGH(thr_parms->tb); TPMBackendCmd cmd = (TPMBackendCmd)data; + bool selftest_done = false; DPRINTF("tpm_passthrough: processing command type %d\n", cmd); switch (cmd) { case TPM_BACKEND_CMD_PROCESS_CMD: tpm_passthrough_unix_transfer(tpm_pt, - thr_parms->tpm_state->locty_data); + thr_parms->tpm_state->locty_data, + &selftest_done); thr_parms->recv_data_callback(thr_parms->tpm_state, - thr_parms->tpm_state->locty_number); + thr_parms->tpm_state->locty_number, + selftest_done); break; case TPM_BACKEND_CMD_INIT: case TPM_BACKEND_CMD_END: diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index a37c7ce..61186c5 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -64,6 +64,7 @@ #define TPM_TIS_STS_TPM_GO (1 << 5) #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4) #define TPM_TIS_STS_EXPECT (1 << 3) +#define TPM_TIS_STS_SELFTEST_DONE (1 << 2) #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1) #define TPM_TIS_BURST_COUNT_SHIFT 8 @@ -147,6 +148,24 @@ static void tpm_tis_show_buffer(const TPMSizedBuffer *sb, const char *string) } /* + * Set the given flags in the STS register by clearing the register but + * preserving the SELFTEST_DONE flag and then setting the new flags. + * + * The SELFTEST_DONE flag is acquired from the backend that determines it by + * peeking into TPM commands. + * + * A VM suspend/resume will preserve the flag by storing it into the VM + * device state, but the backend will not remember it when QEMU is started + * again. Therefore, we cache the flag here. Once set, it will not be unset + * except by a reset. + */ +static void tpm_tis_sts_set(TPMLocality *l, uint32_t flags) +{ + l->sts &= TPM_TIS_STS_SELFTEST_DONE; + l->sts |= flags; +} + +/* * Send a request to the TPM. */ static void tpm_tis_tpm_send(TPMState *s, uint8_t locty) @@ -257,7 +276,8 @@ static void tpm_tis_abort(TPMState *s, uint8_t locty) */ if (tis->aborting_locty == tis->next_locty) { tis->loc[tis->aborting_locty].state = TPM_TIS_STATE_READY; - tis->loc[tis->aborting_locty].sts = TPM_TIS_STS_COMMAND_READY; + tpm_tis_sts_set(&tis->loc[tis->aborting_locty], + TPM_TIS_STS_COMMAND_READY); tpm_tis_raise_irq(s, tis->aborting_locty, TPM_TIS_INT_COMMAND_READY); } @@ -302,7 +322,8 @@ static void tpm_tis_receive_bh(void *opaque) TPMTISEmuState *tis = &s->s.tis; uint8_t locty = s->locty_number; - tis->loc[locty].sts = TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE; + tpm_tis_sts_set(&tis->loc[locty], + TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE); tis->loc[locty].state = TPM_TIS_STATE_COMPLETION; tis->loc[locty].r_offset = 0; tis->loc[locty].w_offset = 0; @@ -322,12 +343,20 @@ static void tpm_tis_receive_bh(void *opaque) /* * Callback from the TPM to indicate that the response was received. */ -static void tpm_tis_receive_cb(TPMState *s, uint8_t locty) +static void tpm_tis_receive_cb(TPMState *s, uint8_t locty, + bool is_selftest_done) { TPMTISEmuState *tis = &s->s.tis; + uint8_t l; assert(s->locty_number == locty); + if (is_selftest_done) { + for (l = 0; l < TPM_TIS_NUM_LOCALITIES; l++) { + tis->loc[locty].sts |= TPM_TIS_STS_SELFTEST_DONE; + } + } + qemu_bh_schedule(tis->bh); } @@ -346,7 +375,7 @@ static uint32_t tpm_tis_data_read(TPMState *s, uint8_t locty) ret = tis->loc[locty].r_buffer.buffer[tis->loc[locty].r_offset++]; if (tis->loc[locty].r_offset >= len) { /* got last byte */ - tis->loc[locty].sts = TPM_TIS_STS_VALID; + tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_VALID); #ifdef RAISE_STS_IRQ tpm_tis_raise_irq(s, locty, TPM_TIS_INT_STS_VALID); #endif @@ -714,7 +743,7 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, break; case TPM_TIS_STATE_IDLE: - tis->loc[locty].sts = TPM_TIS_STS_COMMAND_READY; + tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_COMMAND_READY); tis->loc[locty].state = TPM_TIS_STATE_READY; tpm_tis_raise_irq(s, locty, TPM_TIS_INT_COMMAND_READY); break; @@ -733,7 +762,8 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, /* shortcut to ready state with C/R set */ tis->loc[locty].state = TPM_TIS_STATE_READY; if (!(tis->loc[locty].sts & TPM_TIS_STS_COMMAND_READY)) { - tis->loc[locty].sts = TPM_TIS_STS_COMMAND_READY; + tpm_tis_sts_set(&tis->loc[locty], + TPM_TIS_STS_COMMAND_READY); tpm_tis_raise_irq(s, locty, TPM_TIS_INT_COMMAND_READY); } tis->loc[locty].sts &= ~(TPM_TIS_STS_DATA_AVAILABLE); @@ -755,8 +785,9 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, switch (tis->loc[locty].state) { case TPM_TIS_STATE_COMPLETION: tis->loc[locty].r_offset = 0; - tis->loc[locty].sts = TPM_TIS_STS_VALID | - TPM_TIS_STS_DATA_AVAILABLE; + tpm_tis_sts_set(&tis->loc[locty], + TPM_TIS_STS_VALID| + TPM_TIS_STS_DATA_AVAILABLE); break; default: /* ignore */ @@ -780,7 +811,8 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, val, size); if (tis->loc[locty].state == TPM_TIS_STATE_READY) { tis->loc[locty].state = TPM_TIS_STATE_RECEPTION; - tis->loc[locty].sts = TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID; + tpm_tis_sts_set(&tis->loc[locty], + TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID); } val >>= shift; @@ -796,7 +828,7 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, val >>= 8; size--; } else { - tis->loc[locty].sts = TPM_TIS_STS_VALID; + tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_VALID); } } @@ -809,11 +841,11 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, #endif len = tpm_tis_get_size_from_buffer(&tis->loc[locty].w_buffer); if (len > tis->loc[locty].w_offset) { - tis->loc[locty].sts = TPM_TIS_STS_EXPECT | - TPM_TIS_STS_VALID; + tpm_tis_sts_set(&tis->loc[locty], + TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID); } else { /* packet complete */ - tis->loc[locty].sts = TPM_TIS_STS_VALID; + tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_VALID); } #ifdef RAISE_STS_IRQ if (needIrq) { diff --git a/include/sysemu/tpm_backend.h b/include/sysemu/tpm_backend.h index 825f33b..540ee25 100644 --- a/include/sysemu/tpm_backend.h +++ b/include/sysemu/tpm_backend.h @@ -56,7 +56,7 @@ struct TPMBackend { QLIST_ENTRY(TPMBackend) list; }; -typedef void (TPMRecvDataCB)(TPMState *, uint8_t locty); +typedef void (TPMRecvDataCB)(TPMState *, uint8_t locty, bool selftest_done); typedef struct TPMSizedBuffer { uint32_t size; -- 1.9.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 5/5] tpm: Support for capability flags of TIS 1.3 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger ` (3 preceding siblings ...) 2014-12-09 14:18 ` [Qemu-devel] [PATCH 4/5] tpm: Support for TIS selftest done flag Stefan Berger @ 2014-12-09 14:18 ` Stefan Berger 2014-12-09 14:35 ` [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Michael S. Tsirkin 5 siblings, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:18 UTC (permalink / raw) To: qemu-devel; +Cc: PeterHuewe, Stefan Berger, mst Provide the TIS 1.3 capability flags. The interface now looks like a TIS 1.3 interface. It's fully compatible with previous TIS 1.2 and drivers written for TIS 1.2 continue to work. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> --- hw/tpm/tpm_tis.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index 61186c5..d0bb97f 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -14,7 +14,7 @@ * * Implementation of the TIS interface according to specs found at * http://www.trustedcomputinggroup.org. This implementation currently - * supports version 1.21, revision 1.0. + * supports version 1.3, 21 March 2013 * In the developers menu choose the PC Client section then find the TIS * specification. */ @@ -103,8 +103,15 @@ #endif +#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) +#define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9) +#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) +#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ #define TPM_TIS_CAPABILITIES_SUPPORTED (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ + TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ + TPM_TIS_CAP_DATA_TRANSFER_64B | \ + TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ TPM_TIS_INTERRUPTS_SUPPORTED) #define TPM_TIS_TPM_DID 0x0001 -- 1.9.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger ` (4 preceding siblings ...) 2014-12-09 14:18 ` [Qemu-devel] [PATCH 5/5] tpm: Support for capability flags of TIS 1.3 Stefan Berger @ 2014-12-09 14:35 ` Michael S. Tsirkin 2014-12-09 14:40 ` Stefan Berger 5 siblings, 1 reply; 11+ messages in thread From: Michael S. Tsirkin @ 2014-12-09 14:35 UTC (permalink / raw) To: Stefan Berger; +Cc: PeterHuewe, qemu-devel On Tue, Dec 09, 2014 at 09:18:54AM -0500, Stefan Berger wrote: > The following series of patches extends the TPM TIS implementation to > version 1.3. This will lead to a TIS version that supports TPM 2. > For this I would post relatively small patches afterwards. > > Regards, > Stefan Since this is guest visible, should this be limited to new machine types, to avoid breaking migrating guests across hypervisor versions? > > Stefan Berger (5): > tpm: Extend sts register to 32 bit > tpm: Allow 32 & 16 bit accesses to the registers > tpm: Support for XFIFO register > tpm: Support for TIS selftest done flag > tpm: Support for capability flags of TIS 1.3 > > hw/tpm/tpm_int.h | 1 + > hw/tpm/tpm_passthrough.c | 37 ++++++++++-- > hw/tpm/tpm_tis.c | 131 ++++++++++++++++++++++++++++++++++--------- > hw/tpm/tpm_tis.h | 2 +- > include/sysemu/tpm_backend.h | 2 +- > 5 files changed, 139 insertions(+), 34 deletions(-) > > -- > 1.9.3 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation 2014-12-09 14:35 ` [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Michael S. Tsirkin @ 2014-12-09 14:40 ` Stefan Berger 2014-12-09 14:45 ` Michael S. Tsirkin 0 siblings, 1 reply; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:40 UTC (permalink / raw) To: Michael S. Tsirkin; +Cc: PeterHuewe, qemu-devel On 12/09/2014 09:35 AM, Michael S. Tsirkin wrote: > On Tue, Dec 09, 2014 at 09:18:54AM -0500, Stefan Berger wrote: >> The following series of patches extends the TPM TIS implementation to >> version 1.3. This will lead to a TIS version that supports TPM 2. >> For this I would post relatively small patches afterwards. >> >> Regards, >> Stefan > > Since this is guest visible, should this be limited > to new machine types, to avoid breaking migrating > guests across hypervisor versions? Migration is not currently possible with TPM, since TPM (passthrough) is preventing it. Stefan ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation 2014-12-09 14:40 ` Stefan Berger @ 2014-12-09 14:45 ` Michael S. Tsirkin 2014-12-09 14:48 ` Stefan Berger 2014-12-11 21:15 ` Stefan Berger 0 siblings, 2 replies; 11+ messages in thread From: Michael S. Tsirkin @ 2014-12-09 14:45 UTC (permalink / raw) To: Stefan Berger; +Cc: PeterHuewe, qemu-devel On Tue, Dec 09, 2014 at 09:40:28AM -0500, Stefan Berger wrote: > On 12/09/2014 09:35 AM, Michael S. Tsirkin wrote: > >On Tue, Dec 09, 2014 at 09:18:54AM -0500, Stefan Berger wrote: > >>The following series of patches extends the TPM TIS implementation to > >>version 1.3. This will lead to a TIS version that supports TPM 2. > >>For this I would post relatively small patches afterwards. > >> > >>Regards, > >> Stefan > > > >Since this is guest visible, should this be limited > >to new machine types, to avoid breaking migrating > >guests across hypervisor versions? > > Migration is not currently possible with TPM, since TPM (passthrough) is > preventing it. > > Stefan OK, for live migration, fair enough. For off-line migration: will the following still work: - boot guest with tpm 1.3. use tpm in some way - halt, start guest on old qemu with tpm 1.2 ? ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation 2014-12-09 14:45 ` Michael S. Tsirkin @ 2014-12-09 14:48 ` Stefan Berger 2014-12-11 21:15 ` Stefan Berger 1 sibling, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-09 14:48 UTC (permalink / raw) To: Michael S. Tsirkin; +Cc: PeterHuewe, qemu-devel On 12/09/2014 09:45 AM, Michael S. Tsirkin wrote: > On Tue, Dec 09, 2014 at 09:40:28AM -0500, Stefan Berger wrote: >> On 12/09/2014 09:35 AM, Michael S. Tsirkin wrote: >>> On Tue, Dec 09, 2014 at 09:18:54AM -0500, Stefan Berger wrote: >>>> The following series of patches extends the TPM TIS implementation to >>>> version 1.3. This will lead to a TIS version that supports TPM 2. >>>> For this I would post relatively small patches afterwards. >>>> >>>> Regards, >>>> Stefan >>> Since this is guest visible, should this be limited >>> to new machine types, to avoid breaking migrating >>> guests across hypervisor versions? >> Migration is not currently possible with TPM, since TPM (passthrough) is >> preventing it. >> >> Stefan > OK, for live migration, fair enough. > > For off-line migration: will the following still work: > - boot guest with tpm 1.3. use tpm in some way > - halt, start guest on old qemu with tpm 1.2 > ? So this is not a suspend resume operation ? Sure, it will work if the driver the OS is using works with a TPM TIS 1.3 interface and also with a TPM TIS 1.2 interface. Stefan ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation 2014-12-09 14:45 ` Michael S. Tsirkin 2014-12-09 14:48 ` Stefan Berger @ 2014-12-11 21:15 ` Stefan Berger 1 sibling, 0 replies; 11+ messages in thread From: Stefan Berger @ 2014-12-11 21:15 UTC (permalink / raw) To: Michael S. Tsirkin; +Cc: PeterHuewe, qemu-devel On 12/09/2014 09:45 AM, Michael S. Tsirkin wrote: > On Tue, Dec 09, 2014 at 09:40:28AM -0500, Stefan Berger wrote: >> On 12/09/2014 09:35 AM, Michael S. Tsirkin wrote: >>> On Tue, Dec 09, 2014 at 09:18:54AM -0500, Stefan Berger wrote: >>>> The following series of patches extends the TPM TIS implementation to >>>> version 1.3. This will lead to a TIS version that supports TPM 2. >>>> For this I would post relatively small patches afterwards. >>>> >>>> Regards, >>>> Stefan >>> Since this is guest visible, should this be limited >>> to new machine types, to avoid breaking migrating >>> guests across hypervisor versions? >> Migration is not currently possible with TPM, since TPM (passthrough) is >> preventing it. >> >> Stefan > OK, for live migration, fair enough. > > For off-line migration: will the following still work: > - boot guest with tpm 1.3. use tpm in some way > - halt, start guest on old qemu with tpm 1.2 > ? > > Following my previous comments, are you going to pick up the patches ? Even without others' review? I have more patches to send to the mailing list, but would like to know whether these 5 will make it. Stefan ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-12-11 21:15 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-12-09 14:18 [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 1/5] tpm: Extend sts register to 32 bit Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 2/5] tpm: Allow 32 & 16 bit accesses to the registers Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 3/5] tpm: Support for XFIFO register Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 4/5] tpm: Support for TIS selftest done flag Stefan Berger 2014-12-09 14:18 ` [Qemu-devel] [PATCH 5/5] tpm: Support for capability flags of TIS 1.3 Stefan Berger 2014-12-09 14:35 ` [Qemu-devel] [PATCH 0/5] tpm: Extend the TPM TIS implementation Michael S. Tsirkin 2014-12-09 14:40 ` Stefan Berger 2014-12-09 14:45 ` Michael S. Tsirkin 2014-12-09 14:48 ` Stefan Berger 2014-12-11 21:15 ` Stefan Berger
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