From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59954) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XyedQ-0002ZX-Sr for qemu-devel@nongnu.org; Wed, 10 Dec 2014 05:36:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XyedM-0000M1-2J for qemu-devel@nongnu.org; Wed, 10 Dec 2014 05:36:44 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:35806) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XyedL-0000Lq-T9 for qemu-devel@nongnu.org; Wed, 10 Dec 2014 05:36:40 -0500 From: Bastian Koppelmann Date: Wed, 10 Dec 2014 11:36:29 +0000 Message-Id: <1418211392-21440-7-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1418211392-21440-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1418211392-21440-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 6/9] target-tricore: Make TRICORE_FEATURES implying others. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 1.6), make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way we only need to check our features for the instructionset, where a instruction was first introduced. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/cpu.c | 9 +++++++++ target-tricore/translate.c | 6 +++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c index 7bf041a..abe16fa 100644 --- a/target-tricore/cpu.c +++ b/target-tricore/cpu.c @@ -63,8 +63,17 @@ static bool tricore_cpu_has_work(CPUState *cs) static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); + TriCoreCPU *cpu = TRICORE_CPU(dev); TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev); + CPUTriCoreState *env = &cpu->env; + /* Some features automatically imply others */ + if (tricore_feature(env, TRICORE_FEATURE_16)) { + set_feature(env, TRICORE_FEATURE_131); + } + if (tricore_feature(env, TRICORE_FEATURE_131)) { + set_feature(env, TRICORE_FEATURE_13); + } cpu_reset(cs); qemu_init_vcpu(cs); diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 1daf26d..3775374 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -2206,17 +2206,17 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, case OPC2_32_BO_CACHEI_WI_SHORTOFF: case OPC2_32_BO_CACHEI_W_SHORTOFF: /* TODO: Raise illegal opcode trap, - if tricore_feature(TRICORE_FEATURE_13) */ + if !tricore_feature(TRICORE_FEATURE_131) */ break; case OPC2_32_BO_CACHEI_W_POSTINC: case OPC2_32_BO_CACHEI_WI_POSTINC: - if (!tricore_feature(env, TRICORE_FEATURE_13)) { + if (tricore_feature(env, TRICORE_FEATURE_131)) { tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); } /* TODO: else raise illegal opcode trap */ break; case OPC2_32_BO_CACHEI_W_PREINC: case OPC2_32_BO_CACHEI_WI_PREINC: - if (!tricore_feature(env, TRICORE_FEATURE_13)) { + if (tricore_feature(env, TRICORE_FEATURE_131)) { tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); } /* TODO: else raise illegal opcode trap */ break; -- 2.1.3