From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Subject: [Qemu-devel] [PATCH v3 4/4] target-i386: add Ivy Bridge CPU model
Date: Wed, 10 Dec 2014 14:12:43 -0200 [thread overview]
Message-ID: <1418227963-5807-5-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1418227963-5807-1-git-send-email-ehabkost@redhat.com>
From: Paolo Bonzini <pbonzini@redhat.com>
This is the delta from SandyBridge:
model = 58
stepping = 9
features[FEAT_1_ECX] |=
CPUID_EXT_F16C | CPUID_EXT_RDRAND;
features[FEAT_7_0_EBX] |=
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS;
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 1420993..d8c32d1 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1042,6 +1042,38 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
},
{
+ .name = "IvyBridge",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 58,
+ .stepping = 9,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
+ CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
+ CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_ERMS,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ },
+ {
.name = "Haswell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
--
1.9.3
next prev parent reply other threads:[~2014-12-10 16:13 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-10 16:12 [Qemu-devel] [PATCH v3 0/4] x86 CPU model fixes Eduardo Habkost
2014-12-10 16:12 ` [Qemu-devel] [PATCH v3 1/4] pc: add 2.3 machine types Eduardo Habkost
2014-12-10 16:12 ` [Qemu-devel] [PATCH v3 2/4] target-i386: add VME to all CPUs Eduardo Habkost
2014-12-10 16:12 ` [Qemu-devel] [PATCH v3 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Eduardo Habkost
2014-12-10 16:12 ` Eduardo Habkost [this message]
2014-12-10 16:47 ` [Qemu-devel] [PATCH v3 0/4] x86 CPU model fixes Paolo Bonzini
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