From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j6-00054R-JE for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xz2j5-0007US-BF for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:12 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54567) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j5-0006sg-4i for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:11 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Xz2ip-00019T-Sh for qemu-devel@nongnu.org; Thu, 11 Dec 2014 12:19:55 +0000 From: Peter Maydell Date: Thu, 11 Dec 2014 12:19:33 +0000 Message-Id: <1418300395-4348-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> References: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 11/33] target-arm: implement IRQ/FIQ routing to Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-10-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index d3180dd..973b5a9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4233,12 +4233,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: -- 1.9.1