From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j6-00053m-9I for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xz2j5-0007U7-2W for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:12 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54567) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j4-0006sg-Ro for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:10 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Xz2ip-00019Y-UW for qemu-devel@nongnu.org; Thu, 11 Dec 2014 12:19:55 +0000 From: Peter Maydell Date: Thu, 11 Dec 2014 12:19:34 +0000 Message-Id: <1418300395-4348-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> References: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 12/33] target-arm: add NSACR register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Fabian Aggeler Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-11-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- target-arm/cpu.h | 1 + target-arm/helper.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 532f698..2afe93a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 973b5a9..ace7ef9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ + { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL3_W | PL1_R, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, REGINFO_SENTINEL }; -- 1.9.1