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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 33/33] target-arm: Check error conditions on kvm_arm_reset_vcpu
Date: Thu, 11 Dec 2014 12:19:55 +0000	[thread overview]
Message-ID: <1418300395-4348-34-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org>

From: Christoffer Dall <christoffer.dall@linaro.org>

When resetting a VCPU we currently call both kvm_arm_vcpu_init() and
write_kvmstate_to_list(), both of which can fail, but we never check the
return value.

The only choice here is to print an error an exit if the calls fail.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1418039630-11773-1-git-send-email-christoffer.dall@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/kvm.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index 191e759..4d81f3d 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -442,11 +442,20 @@ bool write_list_to_kvmstate(ARMCPU *cpu)
 
 void kvm_arm_reset_vcpu(ARMCPU *cpu)
 {
+    int ret;
+
     /* Re-init VCPU so that all registers are set to
      * their respective reset values.
      */
-    kvm_arm_vcpu_init(CPU(cpu));
-    write_kvmstate_to_list(cpu);
+    ret = kvm_arm_vcpu_init(CPU(cpu));
+    if (ret < 0) {
+        fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret));
+        abort();
+    }
+    if (!write_kvmstate_to_list(cpu)) {
+        fprintf(stderr, "write_kvmstate_to_list failed\n");
+        abort();
+    }
 }
 
 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
-- 
1.9.1

  parent reply	other threads:[~2014-12-11 12:20 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-11 12:19 [Qemu-devel] [PULL 00/33] target-arm queue Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 01/33] Pass semihosting exit code back to system Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 02/33] Add the "-semihosting-config" option Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 03/33] target-arm: extend async excp masking Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 04/33] target-arm: add async excp target_el function Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 05/33] target-arm: add banked register accessors Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 06/33] target-arm: add non-secure Translation Block flag Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 07/33] target-arm: add CPREG secure state support Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 08/33] target-arm: add secure state bit to CPREG hash Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 09/33] target-arm: insert AArch32 cpregs twice into hashtable Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 10/33] target-arm: move AArch32 SCR into security reglist Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 11/33] target-arm: implement IRQ/FIQ routing to Monitor mode Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 12/33] target-arm: add NSACR register Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 13/33] target-arm: add SDER definition Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 14/33] target-arm: add MVBAR support Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 15/33] target-arm: add SCTLR_EL3 and make SCTLR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 16/33] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 17/33] target-arm: make CSSELR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 18/33] target-arm: make TTBR0/1 banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 19/33] target-arm: make TTBCR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 20/33] target-arm: make DACR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 21/33] target-arm: make IFSR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 22/33] target-arm: make DFSR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 23/33] target-arm: make IFAR/DFAR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 24/33] target-arm: make PAR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 25/33] target-arm: make VBAR banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 26/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 27/33] target-arm: make MAIR0/1 banked Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 28/33] hw/arm/realview.c: Fix memory leak in realview_init() Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 29/33] hw/arm/boot: fix uninitialized scalar variable warning reported by coverity Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 30/33] arm_gic_kvm: Tell kernel about number of IRQs Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 31/33] target-arm/kvm: make reg sync code common between kvm32/64 Peter Maydell
2014-12-11 12:19 ` [Qemu-devel] [PULL 32/33] target-arm: Support save/load for 64 bit CPUs Peter Maydell
2014-12-11 12:19 ` Peter Maydell [this message]
2014-12-11 18:26 ` [Qemu-devel] [PULL 00/33] target-arm queue Peter Maydell

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