From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzPaB-0006vh-O5 for qemu-devel@nongnu.org; Fri, 12 Dec 2014 07:44:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzPZy-0001mO-W0 for qemu-devel@nongnu.org; Fri, 12 Dec 2014 07:44:31 -0500 Received: from mail-wi0-x22f.google.com ([2a00:1450:400c:c05::22f]:43362) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzPZy-0001mH-Pa for qemu-devel@nongnu.org; Fri, 12 Dec 2014 07:44:18 -0500 Received: by mail-wi0-f175.google.com with SMTP id l15so2377661wiw.8 for ; Fri, 12 Dec 2014 04:44:18 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 12 Dec 2014 13:44:02 +0100 Message-Id: <1418388243-1886-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1418388243-1886-1-git-send-email-pbonzini@redhat.com> References: <1418388243-1886-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v3 3/4] serial: update LSR on enabling/disabling FIFOs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: imammedo@redhat.com, andrey@xdel.ru, dgilbert@redhat.com, batuzovk@ispras.ru When the transmit FIFO is emptied or enabled, the transmitter hold register is empty. When it is disabled, it is also emptied and in addition the previous contents of the transmitter hold register are discarded. In either case, the THRE bit in LSR must be set and THRI raised. When the receive FIFO is emptied or enabled, the data ready and break bits must be cleared in LSR. Likewise when the receive FIFO is disabled. Signed-off-by: Paolo Bonzini --- hw/char/serial.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/char/serial.c b/hw/char/serial.c index 4bce268..0a6747c 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -377,12 +377,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, /* FIFO clear */ if (val & UART_FCR_RFR) { + s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); timer_del(s->fifo_timeout_timer); s->timeout_ipending = 0; fifo8_reset(&s->recv_fifo); } if (val & UART_FCR_XFR) { + s->lsr |= UART_LSR_THRE; + s->thr_ipending = 1; fifo8_reset(&s->xmit_fifo); } -- 1.8.3.1