[Qemu-devel] [PATCH 0/8] TriCore add instructions of RR and RR1 opcode format

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Hi,

here is the next patchset for the TriCore ISA, which steadily moves towards being a usable qemu guest.
This patchset first cleans up the SSOV/SUOV makros, which were only suitable for 32 bit arithmetic,
to make room for 16bit SSOV/SUOV arithmetic used for the RR insn. These are splitted into four patches,
seperated by the first opcode all insn of one patch have. I also added missed 1.6 insns and fixed some
minor errors. The last patch adds the first half of the RR1 insn.

Cheers,
Bastian

Bastian Koppelmann (8):
  target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
  target-tricore: Add instructions of RR opcode format, that have 0xb as
    the first opcode
  target-tricore: Add instructions of RR opcode format, that have 0xf as
    the first opcode
  target-tricore: Add instructions of RR opcode format, that have 0x1 as
    the first opcode
  target-tricore: Add instructions of RR opcode format, that have 0x4b
    as the first opcode
  target-tricore: Add missing 1.6 insn of BOL opcode format
  target-tricore: Fix MFCR/MTCR insn and B format offset.
  target-tricore: Add instructions of RR1 opcode format, that have 0xb3
    as first opcode

 target-tricore/helper.h          |   68 +++
 target-tricore/op_helper.c       | 1033 +++++++++++++++++++++++++++++++++++++-
 target-tricore/translate.c       |  900 ++++++++++++++++++++++++++++++++-
 target-tricore/tricore-opcodes.h |   14 +-
 4 files changed, 1992 insertions(+), 23 deletions(-)

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2.1.3