[Qemu-devel] [PULL 00/30] target-mips queue

[Leon Alrae <leon.alrae@imgtec.com>]

Hi,

Here is first MIPS pull request for 2.3.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit dfa9c2a0f4d0a0c8b2c1449ecdbb1297427e1560:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2014-12-15 16:43:42 +0000)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20141216

for you to fetch changes up to d4fa5354a246a1c6cb538a5d8ebcc21206d502fb:

  target-mips: remove excp_names[] from linux-user as it is unused (2014-12-16 12:45:20 +0000)

----------------------------------------------------------------
MIPS patches 2014-12-16

Changes:
* number of bug fixes and minor improvements mainly in microMIPS, mips16
  and gdbstub
* make 5KEf default CPU in 64-bit linux-user
* cleanups

----------------------------------------------------------------
Leon Alrae (4):
      target-mips: convert single case switch into if statement
      disas/mips: remove unused mips_msa_control_names_numeric[32]
      disas/mips: disable unused mips16_to_32_reg_map[]
      target-mips: remove excp_names[] from linux-user as it is unused

Maciej W. Rozycki (26):
      target-mips: Correct the handling of register #72 on writes
      target-mips: Make CP1.FIR read-only here too
      target-mips: Add 5KEc and 5KEf MIPS64r2 processors
      target-mips: Make CP0.Config4 and CP0.Config5 registers signed
      target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors
      target-mips: Enable vectored interrupt support for the 74Kf CPU
      target-mips: Fix formatting in `decode_extended_mips16_opc'
      target-mips: Fix formatting in `mips_defs'
      target-mips: Fix formatting in `decode_opc'
      target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpers
      target-mips: Remove unused `FLOAT_OP' macro
      target-mips: Restore the order of helpers
      target-mips: Correct MIPS16/microMIPS branch size calculation
      target-mips: Correct the handling of writes to CP0.Status for MIPSr6
      target-mips: Correct the writes to Status and Cause registers via gdbstub
      target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP
      target-mips: Output CP0.Config2-5 in the register dump
      target-mips: Fix CP0.Config3.ISAOnExc write accesses
      target-mips: Tighten ISA level checks
      target-mips: Correct 32-bit address space wrapping
      target-mips: gdbstub: Clean up FPU register handling
      target-mips: Also apply the CP0.Status mask to MTTC0
      linux-user: Use the 5KEf processor for 64-bit emulation
      target-mips: Add missing calls to synchronise SoftFloat status
      target-mips: Use local float status pointer across MSA macros
      target-mips: Fix DisasContext's ulri member initialization

 disas/mips.c                 |  10 +-
 linux-user/main.c            |   2 +-
 target-mips/cpu.h            | 124 ++++++++++++-
 target-mips/gdbstub.c        |  56 +++---
 target-mips/helper.c         |  17 +-
 target-mips/helper.h         |   1 +
 target-mips/msa_helper.c     |  69 ++++---
 target-mips/op_helper.c      | 433 ++++++++++++++++++-------------------------
 target-mips/translate.c      | 170 ++++++++++++++---
 target-mips/translate_init.c | 128 +++++++++++--
 translate-all.c              |   2 +-
 11 files changed, 620 insertions(+), 392 deletions(-)