From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0y83-0004E4-DL for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:49:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0y7y-0002M4-U2 for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:49:55 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:6630) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0y7y-0002Ln-MW for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:49:50 -0500 From: Leon Alrae Date: Tue, 16 Dec 2014 19:48:47 +0000 Message-ID: <1418759356-14242-2-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> References: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 01/30] target-mips: Correct the handling of register #72 on writes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Maciej W. Rozycki" From: "Maciej W. Rozycki" Fix an off-by-one error in `mips_cpu_gdb_write_register' for register matching how `mips_cpu_gdb_read_register' handles it. This register slot is a fake anyway, there's nothing in hardware that corresponds to it. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c index f65fec2..7e3a604 100644 --- a/target-mips/gdbstub.c +++ b/target-mips/gdbstub.c @@ -90,7 +90,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return sizeof(target_ulong); } if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >= 38 && n < 73) { + && n >= 38 && n < 72) { if (n < 70) { if (env->CP0_Status & (1 << CP0St_FR)) { env->active_fpu.fpr[n - 38].d = tmp; -- 2.1.0