From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53030) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0yNV-0004uQ-B5 for qemu-devel@nongnu.org; Tue, 16 Dec 2014 15:05:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0yNP-0008Qd-V9 for qemu-devel@nongnu.org; Tue, 16 Dec 2014 15:05:53 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:33061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0yNP-0008QC-C1 for qemu-devel@nongnu.org; Tue, 16 Dec 2014 15:05:47 -0500 From: Leon Alrae Date: Tue, 16 Dec 2014 19:48:50 +0000 Message-ID: <1418759356-14242-5-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> References: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 04/30] target-mips: Make CP0.Config4 and CP0.Config5 registers signed List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Maciej W. Rozycki" From: "Maciej W. Rozycki" Make the data type used for the CP0.Config4 and CP0.Config5 registers and their mask signed, for consistency with the remaining 32-bit CP0 registers, like CP0.Config0, etc. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c01bbda..a08c2c8 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -446,8 +446,8 @@ struct CPUMIPSState { #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 - uint32_t CP0_Config4; - uint32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 #define CP0C4_KScrExist 16 @@ -456,8 +456,8 @@ struct CPUMIPSState { #define CP0C4_FTLBWays 4 #define CP0C4_FTLBSets 0 #define CP0C4_MMUSizeExt 0 - uint32_t CP0_Config5; - uint32_t CP0_Config5_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31 #define CP0C5_K 30 #define CP0C5_CV 29 -- 2.1.0